Zynq-7000-based anti-single event upset protection method for on-chip memory

Abstract

The invention relates to a Zynq-7000-based scratch-pad memory single event upset protection method which is applied to a memory fault-tolerant design of Zynq-7000SoC in a space environment, and aims to solve the problems that single event upset affects data reliability of a memory on an internal pad of a Zynq-7000 chip in a space environment. Correct communication between dual-core processors in the Zynq-7000 chip is guaranteed. On the basis of resource characteristics of the Zynq-7000 chip, data reinforcing operation of communication between the dual-core processors and the scratch-pad memory is realized by a software EDAC method, state tags of a single-bit error and a dual-bit error and dual-core synchronous write-back operation of the single-bit error are realized by a software interruption mode, and functions of single-error-correcting and double-error-detecting and data write-back of data are fulfilled in an ARM processor, therefore, the single event upset resistance of the memory on the internal pad of Zynq-7000 is improved, and an important means is provided for reliability of data communication between the dual-core processes in Zynq-7000 SoC.

Description

technical field [0001] The invention relates to the field of software methods, and is specifically applied to on-board systems, in particular to a Zynq-7000-based on-chip memory anti-single event reversal protection method. Background technique [0002] In recent years, commercial-off-the-shelf (COTS) devices have been increasingly used in the aerospace field due to their low cost, high performance, and no restrictions on foreign imports. Among them, Xilinx's Zynq-7000 series devices tightly integrate dual-core ARM processors with programmable logic and hard IP peripherals. The perfect combination of flexibility and configurability has attracted widespread attention in the field of small satellites and is gradually applied in the aerospace field. in engineering practice. [0003] The dual-core ARM Cortex-A9 processor in the PS part of the Zynq-7000SoC can use an asymmetric multi-processing (Asymmetric Multi-core Processor, AMP) mechanism to execute different tasks in parall...

AI Technical Summary

Problems solved by technology

Among them, the processor's built-in EDAC circuit is usually determined by the security level of the chip, such as an aerospace-grade chip, while the on-chip memory in the Zynq-7000 only has a parity check function, does not have error correction capabilities, and does not meet the anti-single event requirements of the spaceborne system. Requirements for inversion; the realization of EDAC circuits with FPGA has the characteristics of flexible design and configurability, but as a volatile storage, SRAM-type FPGA has its own reliability problems, and the most important thing is that the dual-core processor and the on-chip memory have been integrated in the same In the chip, the hardening of the memory cannot be realized through the external hardware EDAC circuit

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