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A pointer logic address mapping table implementation method for nand Flash

A technology of logical address and implementation method, applied in the field of pointer logic address mapping table implementation, can solve the problems of complex control of memory chips, and achieve the effect of avoiding garbage collection algorithm and wear leveling algorithm, reducing implementation difficulty and avoiding implementation.

Active Publication Date: 2020-06-09
SHANDONG INSPUR SCI RES INST CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Most of the new high-speed hard disks use NandFlash chips as storage media, but the control of this storage chip is complex and requires control mechanisms such as garbage collection and wear leveling

Method used

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Embodiment Construction

[0017] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention clearer, the present invention will be described in detail below in conjunction with the embodiments. It should be noted that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

[0018] The implementation method of the pointer logic address mapping table for NandFlash comprises the following steps:

[0019] (1) Establish a first-level logical address mapping table, the address of each entry in the first-level logical address mapping table is a logical address, and the content stored in the entry is a first-level physical address;

[0020] (2) According to the NandFlash chip specification, a free block physical address sub-table is established for each plan (planning);

[0021] (3) sequentially read the bad block information of each block (block) of the NandFlash memory chip, an...

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Abstract

The invention particularly relates to a pointer-type logic address mapping table realizing method for Nand Flash. A multilevel logic address mapping table of single logic addresses is realized by using an address pointer, high time cost caused by garbage collection when a Nand Flash chip has writing errors is lowered, realizing of complex garbage collection algorithm and wear leveling algorithm is avoided, realizing difficulty of a Nand Flash controller is lowered effectively, and storage writing-in speed is increased.

Description

technical field [0001] The invention relates to the technical field of NandFlash controllers, in particular to a method for realizing a pointer logic address mapping table for NandFlash. Background technique [0002] With the continuous development of computer technology, the capacity and speed of storage devices have been greatly improved. Most of the new high-speed hard drives use NandFlash chips as storage media, but the control of this storage chip is complex, requiring control mechanisms such as garbage collection and wear leveling. [0003] Based on the above situation, the present invention proposes a method for implementing a pointer logic address mapping table for NandFlash. The purpose is to realize the multi-level logical address mapping table for a single logical address by using the address pointer, thereby reducing the high time cost caused by garbage collection when a write error occurs in the NandFlash chip. Contents of the invention [0004] In order to ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F12/02G06F12/06
CPCG06F12/0292G06F12/0653
Inventor 赵鑫鑫姜凯李朋尹超
Owner SHANDONG INSPUR SCI RES INST CO LTD