Settling time test method and system for digital to analog converter

A technology of digital-to-analog converter and settling time, applied in the direction of analog/digital conversion calibration/test, analog/digital conversion, code conversion, etc., can solve problems affecting product development progress and achieve the effect of setting up time

Active Publication Date: 2017-12-29
SEMICON MFG INT TIANJIN +1
View PDF3 Cites 2 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

If all manual testing is done, the completion of the entire testing cycle will seriously affect the product development progress

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Settling time test method and system for digital to analog converter
  • Settling time test method and system for digital to analog converter
  • Settling time test method and system for digital to analog converter

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0059] figure 1 For the waveform diagram of the measured data output by the digital-to-analog converter, the prior art cannot automatically test the setup time of the digital-to-analog converter, and manual identification is required based on the measured data output by the digital-to-analog converter. The inventor studied the setup time and the waveform output by the digital-to-analog converter and found that in one sampling period, such as figure 2 Shown (in figure 2 Where the abscissa is the time time, the ordinate is the voltage amplitude (amplitude), after the voltage overshoot (overshoot), after the end of the voltage oscillation, enters the high-level stable interval a, in the high-level stable interval a, the voltage The average value is the high level average value VHmean. After the overshoot (overshoot), the first time the voltage value is the high-level average value VHmean sampling point is the setup time start point P1X, the high-level stable interval a starts at ...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

PUM

No PUM Login to view more

Abstract

The invention discloses a settling time test method for a digital to analog converter. The method comprises the steps of sampling an electrical signal of the digital to analog converter; acquiring an average high level value in a sampling period according to sampled data; acquiring a stable high level section after voltage oscillation ends; finding an initial sampling point of the stable high level section in the sampled data, and recording the initial sampling point as a settling time end point; finding the longest voltage value continuous raising section in the sampled data, and recording the section as a maximum raising section; finding the first sampling point of which the voltage value is the average high level value from the sampled data after the maximum raising section ends, and recording the first sampling point as a settling time initial point; and acquiring settling time according to the settling time initial point and the settling time end point. The invention also provides a settling time test system for the digital to analog converter using the method, and thus the settling time can be automatically tested.

Description

Technical field [0001] The present invention relates to the technical field of digital-to-analog converter testing, in particular to a method and system for testing the establishment time of a digital-to-analog converter. Background technique [0002] For the characteristic analysis test of DAC (digital-to-analog converter), including the test of settling time, the settling time is the time required for an oscillating signal to stabilize to a specified final value. However, the current settling time test requires a lot of manual identification. With the development of chip technology, it is necessary to make a comprehensive evaluation of the chip under different voltage, temperature, and speed conditions. At the same time, it is also necessary to test a larger number of samples, which brings new challenges to the test work. If all the tests are done manually, the completion of the entire test cycle will seriously affect the development progress of the product. Therefore, it is ...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

Application Information

Patent Timeline
no application Login to view more
Patent Type & Authority Applications(China)
IPC IPC(8): H03M1/10
CPCH03M1/1095
Inventor 刘琦刘朋
Owner SEMICON MFG INT TIANJIN
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap