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Minimum height cmos image sensor

A technology of image sensors and sensor tubes, applied in image communication, semiconductor devices, electric solid-state devices, etc., can solve the problem of edge-mounted sensors

Active Publication Date: 2021-12-28
HAND HELD PRODS
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This can be especially problematic for edge-mounted sensors such as imaging barcode scanners

Method used

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  • Minimum height cmos image sensor
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  • Minimum height cmos image sensor

Examples

Experimental program
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Embodiment Construction

[0032] Prior art CMOS image sensors generally have figure 1The layout depicted in . In general, a prior art CMOS sensor (10) has a layout of components on a sensor die (11), including a sensor array (12), an analog-to-digital (ADC) module (13), digital logic ( 4), timing and control panel (5), analog signal processing module (17), and may include bond pads (18) around the perimeter of the sensor die (11). As can be seen from the figures, the prior art sensor array ( 12 ) is not centralized on the sensor die ( 11 ).

[0033] The present invention covers a CMOS image sensor for a camera assembly having a sensor array concentrated on a sensor die and having a small footprint.

[0034] In an exemplary embodiment, refer to figure 2 , a CMOS image sensor (200) is provided. figure 2 The particular example has a minimum height. The CMOS sensor (200) has a sensor die (21) that holds the other components of the sensor. The sensor die ( 21 ) has a set of opposing faces ( 22 ), th...

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PUM

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Abstract

The present application relates to a minimum height CMOS image sensor, wherein a CMOS image sensor for a camera assembly is provided having a sensor die with opposing faces, upper and lower. On top, the sensor die is provided with a sensor array, an analog-to-digital conversion module, digital logic circuits, and timing and clock control circuits. The sensor array is basically centered on the sensor die. The analog-to-digital conversion module is divided into two sub-modules. Each sub-module is disposed adjacent to and positioned on opposite sides of the sensor array. Digital logic circuits form the first row. Timing and clock control circuits and analog signal processing circuits are adjacent and form a second row. The first and second rows are of similar size and are disposed on opposite sides of the sensor array.

Description

technical field [0001] The present invention relates to complementary metal oxide semiconductor (CMOS) image sensors. Background technique [0002] In general, the layout of a sensor die for a CMOS image sensor includes a sensor array, an analog-to-digital (ADC) module, digital logic circuits, and a timing and control plane. The sensor array is not centered on the sensor die in order to keep like components together. Optimizing the sensor die layout design to keep similar components together allows several advantages. For example, an ADC module in a conventional image sensor outputs in a line-to-line image digital format, which is compatible with conventional image display devices. However, there are adverse consequences to these layout designs. Sacrifice, for example, centers sensor arrays on the die to keep similar components together. Additionally, the possibility of a smaller footprint for sensors threatens convention by keeping similar components together. This can...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04N5/374H04N5/376H04N5/378H04N25/42
CPCH04N25/766H04N25/76H04N25/78H01L27/14607H01L27/14634H01L27/14636H01L27/14645H04N25/79H04N25/75H04N25/42H04N25/745
Inventor 冯琛E.C.布雷默T.冼P.A.焦尔达诺S.P.基尔尼P.波罗尼维奇
Owner HAND HELD PRODS