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A multi-level cache and cache method based on ssd RAID array

A technology of caching and mapping tables, applied in memory systems, instruments, input/output to record carriers, etc., can solve problems such as the increase in data error rate, reduce data update and delayed verification, prolong SSD life, reduce costs and The effect of error rate

Active Publication Date: 2020-05-19
HUAZHONG UNIV OF SCI & TECH
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  • Abstract
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  • Application Information

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Problems solved by technology

This solves the problem of increased data error rate in the existing SSD RAID life extension technology

Method used

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  • A multi-level cache and cache method based on ssd RAID array
  • A multi-level cache and cache method based on ssd RAID array
  • A multi-level cache and cache method based on ssd RAID array

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Embodiment Construction

[0047] In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention, but not to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0048] Some definitions will be used in the embodiments of the present invention, and the nouns therein are explained as follows:

[0049] Page: is the basic unit of the upper-layer cache in the present invention, and the compressed data and its metadata are stored in the integrated layer page;

[0050] Stripe: is the unit for writing data from the upper layer cache to the lower layer in the presen...

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Abstract

The invention discloses a multilevel cache based on an SSD RAID array and a caching method and belongs to the field of solid state disk storage technology. The multilevel cache is designed, wherein anupper-layer cache is realized through a small-capacity NVRAM and is responsible for compressing data, backing up the data to a DRAM, integrating the compressed data and metadata of the compressed data into a page for storage and scheduling the data to a lower-layer cache with stripes being units; and the lower-layer cache is realized by separating a part of space from an RAID and is responsible for caching the compressed data, maintaining a mapping table of the original data and the compressed data, restoring the compressed data to the RAID and performing power-fail recovery on the mapping table. The multilevel caching method based on the SSD RAID array is also implemented. Through the technical scheme, according to the characteristic that redundancy between new data and old data is large, the compressed data is managed and stored in the multilevel cache, the demand for cache capacity is reduced, and the cost and the error rate are lowered; and multilevel cache design ensures system reliability, and regardless of the DRAM, the NVRAM or the RAID, timely recovery can be realized in case of data loss or errors.

Description

technical field [0001] The invention belongs to the technical field of solid-state hard disk storage, and more particularly, relates to a multi-level cache and a cache method based on an SSD RAID array. Background technique [0002] Flash-based solid state disks (Solid State Drives, SSD) have been widely used in enterprise-level storage due to their excellent performance, non-isolation, and low power consumption. However, flash memory has the defect of limited life, and there are reliability problems when flash memory is applied to large-scale storage systems. Using the Redundant Arrays of Independent Disks (RAID) technology to build a large-scale flash memory array can not only increase the capacity of the storage system, improve performance, but also ensure reliability. [0003] But the introduction of RAID will further shorten the life of SSD. Every data update is accompanied by a checksum update, and frequent updates will trigger garbage collection and data block erasu...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F3/06G06F12/0897
Inventor 万胜刚叶蕊孟文韬
Owner HUAZHONG UNIV OF SCI & TECH
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