Verification Method of Processor Random Instruction Multiplexing

Abstract

The invention provides a verification method of processor random instruction reusability. The verification method includes: running a reference model and reading a binary iss.vmem instruction file into an associative array dut_mem and iss_mem; when the address, of instructions or the associative array of the reference model does not exist, randomly generating the instructions or data and respectively filling the instructions or data into the dut_mem and the iss_mem; running a processor, reading mem_dut through an external slave memory model, and when a non-existing address is read by the processor, filling in the dut_mem with random instructions continuously; after running of the processor is completed, writing the dut_mem into dut.mem, and storing the address of the dut_mem and corresponding data; reading the dut.mem to execute the next running of the processor. With the method, the instructions and the data that truly needed by the processor can be generated randomly, and good reusability is achieved.

Description

technical field [0001] The invention relates to the technical field of processors, in particular to a verification method for multiplexing random instructions of a processor. Background technique [0002] The processor is the core of the chip, and the correctness of its function is often crucial. In particular, every redesigned or modified processor needs to go through a lot of regression tests, and even multiple tape-outs before it can be actually used in the project. . Therefore, the verification of the processor usually requires a lot of time and human investment. [0003] The traditional incentive is a hand-written C program, and the compiler generates a binary code that the processor can recognize, and the processor reads this binary code to run; or establish a random incentive environment, with a reference model verification environment that is synchronized with the processor Running, data comparison is performed synchronously when the command is submitted. [0004]...

AI Technical Summary

Problems solved by technology

This method has reusability, but the randomness is poor, and it cannot fully cover the various possible states of the processor.

Or use a random instruction environment for testing. Since modern processors have branch prediction and cache, when the previous instruction is not completed, it needs to be pre-fetched and executed in advance. Before the instruction is running, it needs PC and memory access of random instructions. The address cannot be determined. When the processor accesses the same address again, the corresponding instruction may still be in the cache. At this time, if another instruction is randomly generated again, the comparison between the corresponding golden without cache and the processor will be wrong.

Therefore, it is not possible to randomly generate instructions in real time and then send the generated instructions to the processor

So this incentive environment is not suitable for processor verification with cache, and the reusability is poor

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