A 3D NAND memory hierarchical layer stack manufacturing method

Abstract

The invention relates to a method for manufacturing a 3D NAND memory level stack, the method comprising the following steps: forming an oxide / nitride level layer stack on a silicon substrate, and then forming a layer vertically penetrating through the oxide / nitride level layer stack Gate line slits; removing the nitride layer in the oxide / nitride level layer stack to form a recessed area; using hydrofluoric acid to etch back the recessed area so that the oxidation in the oxide / nitride level layer stack flattening the surface of the object layer; filling the conductor material into the recessed area to form a conductor layer and etching the conductor layer to form a conductor / insulator level layer stack. The 3D NAND memory level layer stack manufacturing method of the present invention can eliminate the oxide layer bulk phenomenon by using hydrofluoric acid (HF) to etch back the bulk structure, thereby improving the filling rate of the conductor layer in the 3D NAND level layer stack, and then improving the device. performance.

Description

technical field [0001] The invention relates to a method for manufacturing a hierarchical layer stack of a 3D NAND memory, and relates to the technical field of 3D NAND memory manufacturing. Background technique [0002] With the development of semiconductor technology, various semiconductor memory devices have been proposed. Compared with conventional storage devices such as magnetic storage devices, semiconductor storage devices have the advantages of fast access speed and high storage density. Among them, the NAND structure is receiving more and more attention. To further increase storage density, various three-dimensional (3D) NAND devices have emerged. [0003] Such as Figure 1A As shown in -C, it is a schematic diagram of the prior art 3D NAND memory level layer stack manufacturing process. Specifically include the following steps: [0004] (1) if Figure 1A As shown, a hierarchical layer stack 103 is formed on a silicon substrate 101, and a gate line slit 102 (Ga...

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Problems solved by technology

[0010] When the etch rate is low, such as Figure 1B Shown, oxide tends to re-grow during step (2), and the excess oxide (thickness about 5-10 angstrom of thickness, 1 angstrom=10 -10 m), leading to the formation of the oxide layer 104 of the big head phenomenon ( Figure 1B shown in the circles of ), which in turn will lead to the formation of bubbles or voids 108 in step (3), which is a phenomenon that is undesirable or wants to be avoided in the manufacture of NAND devices, because such bubbles or voids will eventually lead to The metal tungsten layer opens or the resistance value increases, which seriously affects the device performance

[0011] Usually this big head phenomenon is difficult to avoid, because the silicon concentration in the phosphoric acid material is difficult to control, because when the silicon nitride layer is removed by etching, the silicon concentration will increase

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