Phosphoric acid cleaning control device and method

Abstract

The invention relates to a phosphoric acid cleaning control device and method. The device comprises the following structures: a first controller which is connected with a silicon monitor, an air valveand a second controller; the second controller which is connected with a phosphoric acid circulation loop and the first controller and used for controlling discharge of the liquid phosphoric acid medicine in the phosphoric acid circulation loop; the silicon monitor which is connected with the phosphoric acid circulation loop and used for monitoring the silicon concentration in the phosphoric acidcirculation loop and feeding the silicon concentration back to the first controller; the air valve which is connected with the first controller and the phosphoric acid circulation loop and controls supplementing of the liquid phosphoric acid medicine in the phosphoric acid circulation loop; and the phosphoric acid circulation loop which leads in the liquid phosphoric acid medicine from the air valve to clean the 3D NAND memory hierarchical stack to be processed. According to the phosphoric acid cleaning control device and method, the silicon concentration is automatically monitored and controlled in real time, the silicon concentration can be maintained and the large-headed phenomenon of the oxide layer can be eliminated so that the filling yield rate of the conductor layer in the 3D NANDhierarchical stack can be enhanced and the device performance can be enhanced.

Description

technical field [0001] The invention relates to a phosphoric acid cleaning control device and method, and relates to the technical field of 3D NAND memory manufacturing. Background technique [0002] With the development of semiconductor technology, various semiconductor memory devices have been proposed. Compared with conventional storage devices such as magnetic storage devices, semiconductor storage devices have the advantages of fast access speed and high storage density. Among them, the NAND structure is receiving more and more attention. To further increase storage density, various three-dimensional (3D) NAND devices have emerged. [0003] Such as Figure 1A As shown in -C, it is a schematic diagram of the prior art 3D NAND memory level layer stack manufacturing process. Specifically include the following steps: [0004] (1) if Figure 1A As shown, a hierarchical layer stack 103 is formed on a silicon substrate 101, and a gate line slit 102 (Gate Line Slit, GLS) is...

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Problems solved by technology

[0013] However, this device and cleaning control method has the following problems: it calculates the amount of phosphoric acid dripped or supplied by the ELC to control the silicon concentration based on the silicon nitride pre-value of the product process, and cannot monitor and control the silicon concentration in the phosphoric acid liquid in real time.

If the silicon concentration is not well controlled, as mentioned earlier, the silicon concentration is too low and the oxide layer will also be etched away, and if the silicon concentration is too high, the oxide layer will appear bulky, resulting in abnormal subsequent processes

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