Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

A three-dimensional stacked integrated structure and its multi-chip integrated structure and preparation method

A multi-chip integration and chip technology, which is applied in semiconductor/solid-state device manufacturing, semiconductor/solid-state device components, semiconductor devices, etc., can solve the problem of high interface leakage, achieve good passivation performance, high vertical interconnection density, and conductance high rate effect

Active Publication Date: 2022-02-22
XIAN MICROELECTRONICS TECH INST
View PDF10 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Although the use of polymer as the insulating material for the hole wall of the conductive via hole on the silicon substrate has the advantage of low cost, it is only suitable for the conductive via hole with a large aperture, and the high-density interface state between the silicon and the polymer exists, and the interface leakage is relatively large. high

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • A three-dimensional stacked integrated structure and its multi-chip integrated structure and preparation method
  • A three-dimensional stacked integrated structure and its multi-chip integrated structure and preparation method
  • A three-dimensional stacked integrated structure and its multi-chip integrated structure and preparation method

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0063] The present invention is a multi-chip integrated structure. A plurality of chips are buried in a substrate with conductive through holes to form a structure of reconstructed chips. The substrate can be silicon or glass; when the substrate shown is a silicon base In the case of sheet 1, the conductive via is a conductive via 17 passing through silicon, that is, a TSV (Through-Silicon-Via) hole; when the substrate shown is a glass substrate 31, the conductive via is through The conductive through hole 32 of the glass, that is, the TGV (Through-Glass-Via) hole;

[0064] There are external pin arrays on the upper and lower surfaces of the above-mentioned reconstructed chip, and at the same time, according to product requirements, the pins in the external pin arrays on the upper and lower surfaces can be electrically connected.

[0065] Taking the silicon wafer as the substrate as an example, it includes:

[0066] First, a conductive blind hole 4 is prepared on one side of ...

Embodiment 2

[0116] A kind of multi-chip integrated structure of the present invention, the substrate that embeds chip can be glass substrate 31, as attached Figure 14 As shown, is a schematic cross-sectional view of a glass-based reconstitution chip 300,

[0117] The first chip 13 and the second chip 14 are respectively buried in a glass substrate 31 with conductive vias (TGV) 32 passing through the glass to form a glass-based reconstitution chip 300 . Because the glass is transparent and has good high-frequency characteristics, the embedding and reconstruction of chips in the glass substrate 31 has great application potential in high-frequency high-speed, microwave, radio frequency circuits and optoelectronic systems;

[0118]Wherein, because the glass is not conductive, no additional dielectric insulating layer is needed between the conductive via (TGV) 32 passing through the glass on the glass substrate 31 and the glass substrate 31;

[0119] The groove 30 embedded in each chip on th...

Embodiment 3

[0122] A three-dimensional stacked integrated structure in the present invention, such as Figure 15 shown.

[0123] After two or more of the above-mentioned multi-chip reconfigured chips are stacked and bonded, multi-chip three-dimensional integration can be formed; the above-mentioned multi-chip reconfigured chips can also be used as an active transfer substrate, and ordinary chips can also be directly bonded to The above-mentioned multi-chip is reconstructed on the chip to form a three-dimensional integration. The bonding of ordinary chips on the above-mentioned multi-chip two-dimensional reconstruction integrated chip can be flip-chip (Flip-Chip) bonding or wire bonding, as follows:

[0124] The reconstructed chip formed by embedding the chip in a substrate with conductive through holes has an array of external pins on its upper and lower surfaces, and at the same time, according to product requirements, the pins in the array of external pins on the upper and lower surfac...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

PropertyMeasurementUnit
Thicknessaaaaaaaaaa
Thicknessaaaaaaaaaa
Thicknessaaaaaaaaaa
Login to View More

Abstract

The invention relates to a three-dimensional stacked integrated structure and its multi-chip integrated structure and preparation method, comprising a substrate and a number of chips embedded in the substrate; the substrate is provided with a number of conductive through holes penetrating the front and back of the substrate, and the substrate is connected to the substrate. Conductive through-holes that are insulated are filled with conductive materials; the back of the substrate is provided with several grooves at intervals, each groove is embedded with a corresponding chip, and the chip pads on the front of the chip face the back of the substrate; the surfaces on the back of the substrate are arranged in sequence There are electrically connected back multilayer metal wiring layers, back UBM layers and back external electrical pins, and the front surface of the substrate is sequentially provided with electrically connected front multilayer metal wiring layers, front UBM layers and front The external electrical pins form the electrical connection in the horizontal direction of the multi-chip integrated structure; realize the high-density, high-performance, and highly reliable three-dimensional TSV stack integration of multiple chips, and solve multiple chips with different functions, different sizes, different materials, and different processes 3D integration problem.

Description

technical field [0001] The invention relates to the technical field of advanced electronic packaging, in particular to a three-dimensional stacked integrated structure, a multi-chip integrated structure and a preparation method thereof. Background technique [0002] While the demand for diversified and complex functions of electronic systems is gradually increasing, the volume, power consumption, and weight of electronic systems are required to be further reduced, which promotes the rapid development of electronic integration technology. After years of research and development, SOC (System-on-Chip) "system on a chip" is a monolithic integration technology. Although great progress has been made, the understanding of its disadvantages and limitations has gradually become clear. Especially limited by the manufacturing process of semiconductor wafers, many functional chips, such as radio frequency chips, photoelectric chips, sensor chips, power chips, etc., are not compatible wi...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
IPC IPC(8): H01L25/065H01L21/98H01L23/498H01L23/528H01L23/532H01L23/538H01L21/50H01L21/768
CPCH01L25/0655H01L25/0652H01L25/50H01L23/528H01L23/5384H01L23/5386H01L23/5389H01L23/5329H01L23/53228H01L23/49805H01L23/49827H01L23/49838H01L21/50H01L21/76831H01L21/76879H01L2221/1057H01L2221/1068H01L2224/18H01L2224/73267H01L2224/32225H01L2224/92244H01L2224/12105H01L2224/04105H01L2924/15153H01L2225/1035H01L2225/1058H01L2225/1041H01L2225/1094H01L2224/16227H01L2924/15311H01L2924/15192
Inventor 李宝霞
Owner XIAN MICROELECTRONICS TECH INST
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com