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Analysis method for n electrode pattern of efficient vertical-structure LED chip

A LED chip, vertical structure technology, applied in the direction of electrical digital data processing, special data processing applications, instruments, etc., to achieve the effect of simple method, reduced sample quantity, and strong applicability

Inactive Publication Date: 2018-03-16
SOUTH CHINA UNIV OF TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0003] However, different n-electrode patterns will cause different effects on current distribution, and the distribution of current has a decisive effect on the distribution of light-emitting area.

Method used

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  • Analysis method for n electrode pattern of efficient vertical-structure LED chip
  • Analysis method for n electrode pattern of efficient vertical-structure LED chip
  • Analysis method for n electrode pattern of efficient vertical-structure LED chip

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Embodiment 1

[0046] A method for analyzing the n-electrode pattern of an efficient vertical structure LED chip, comprising the following steps:

[0047] (1) Construct the substrate of the LED chip model: use the modeling function of Tracepro software to construct the Si substrate, the substrate size is 120um×80um×120um, and it is in the shape of a cuboid; the height is 80um;

[0048] (2) Construct the p-electrode layer of the vertical structure LED chip model: use the 3D modeling function of Tracepro software to sequentially construct the bonding layer, the p-electrode protective layer, and the mirror on the silicon substrate (the surface with the same length and width): bonding The size of the layer is 120um×5um×120um, the size of the protective layer of the p electrode plate is 120um×10um×120um, and the size of the mirror is 120um×300nm×120um; each size refers to length×height×width;

[0049] (3) Construct the epitaxial layer of the vertical structure LED chip model: use the Tracepro sof...

Embodiment 2

[0064] A method for analyzing the n-electrode pattern of an efficient vertical structure LED chip, comprising the following steps:

[0065] (1) Construct the substrate of the LED chip model: use the modeling function of Tracepro software to construct the Si substrate, the substrate size is 120um×80um×120um, and it is in the shape of a cuboid; the height is 80um;

[0066] (2) Construct the p-electrode layer of the vertical structure LED chip model: use the 3D modeling function of Tracepro software to sequentially construct the bonding layer, the p-electrode protective layer, and the mirror on the silicon substrate (the surface with the same length and width): bonding The size of the layer is 120um×5um×120um, the size of the protective layer of the p electrode plate is 120um×10um×120um, and the size of the mirror is 120um×300nm×120um; each size refers to length×height×width;

[0067] (3) Construct the epitaxial layer of the vertical structure LED chip model: use the Tracepro sof...

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Abstract

The invention belongs to the LED technical field and discloses an analysis method for an n electrode pattern of an efficient vertical-structure LED chip. The method comprises the steps that (1) Tracepro software is adopted to construct a substrate, a p electrode layer and an epitaxial layer of a vertical-structure LED chip model in sequence, the n electrode pattern is drawn, a contact target surface is constructed, material parameters and a light source are set, light emission efficiency of the LED chip model is analyzed, record data is collected, and pattern parameters are optimized; (2) multiple vertical-structure LED chip models with different electrode patterns are constructed according to the step (1), light data of all the models is subjected to comparative analysis, and the electrode pattern with optimal external quantum efficiency is obtained; (3) the n electrode pattern is formed on the surface of the vertical-structure LED chip; and (4) performance testing is performed, comparison with a simulated result is performed, and a conclusion is obtained. The method is efficient, the n electrode pattern corresponding to the LED chip with excellent performance can be obtained in ashort time, time is saved, and cost is lowered.

Description

technical field [0001] The present invention relates to an efficient method for analyzing the n-electrode pattern of a vertically structured LED chip, in particular to combining the Tracepro simulation of different n-electrode patterns with the preparation of LED chips, and providing an efficient analysis method for the n-electrode pattern of a vertically structured LED chip method. Background technique [0002] As a new type of solid-state light source, LED has the advantages of energy saving, environmental protection, longevity, safe use of low voltage and diverse shapes. The traditional LED is a horizontal structure LED prepared on a sapphire substrate. Since the sapphire substrate is non-conductive, Therefore, the current is transmitted laterally in the epitaxial layer, and the p-electrode and n-electrode are on the same side. It is necessary to etch p-GaN to prepare the p-electrode, which not only reduces the light-emitting area, but also increases the shading area due ...

Claims

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Application Information

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IPC IPC(8): G06F17/50
CPCG06F30/367
Inventor 李国强张云鹏张子辰蔡鸿张啸尘黄裕贤
Owner SOUTH CHINA UNIV OF TECH
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