Frequency demultiplication adjustment method of PLL

Abstract

The invention provides a frequency demultiplication adjustment method of PLL, applied to an embedded system. The method comprises the following steps: obtaining a plurality of corresponding frequencydemultiplication frequency points according to a default frequency demultiplication value of a phase-locked loop; obtaining, by a processor frequency adjustor, a load state of a processor within a predetermined sampling period, and obtaining a target frequency point of the processor according to the load state; determining a frequency range of a virtual frequency point to be added according to theposition of target frequency between the frequency points; performing calculation within the frequency range to obtain equivalent frequency corresponding to a plurality of virtual frequency points; judging whether the frequency of the target frequency point is equal to the equivalent frequency corresponding to the virtual frequency points; if not, switching the processor frequency adjustor to thecorresponding frequency demultiplication frequency point; and adjusting the frequency demultiplication value of the phase-locked loop, so that the phase-locked loop outputs a clock source signal corresponding to the virtual frequency points to the processor. The problems that after the phase-locked loop is fixed, the available frequency points are insufficient and the frequency corresponding to the frequency points has greater difference in the prior art are solved.

Description

technical field [0001] The invention relates to the field of communication technology, in particular to a PLL frequency division adjustment method. Background technique [0002] DVFS (Dynamic Voltage and Frequency Scaling, dynamic voltage frequency adjustment method,) is a very important function of the embedded system, mainly according to the different needs of the computing power of the application program running on the chip, dynamically adjust the operating frequency and voltage of the chip (for The same chip, the higher the frequency, the higher the voltage required), so as to achieve the purpose of energy saving. The frequency point required for the operation of the processor (CPU, Central Processing Unit) is generally supported by the PLL (Phase Locked Loop, Phase Locked Loop) designed by the chip, so that the CPU can run in a wide frequency range from tens of MHz to 2GHz. Due to the wide range of frequency bands mentioned above, most chip implementations use multipl...

AI Technical Summary

Problems solved by technology

Due to the wide range of frequency bands mentioned above, most chip implementations use multiple PLLs. When the frequency is low, it runs on one PLL, and when the frequency is high, it switches to another PLL. However, this processing method There are the following defects. If the load of the running program changes drastically, the CPU’s operating clock source may switch back and forth between the two PLLs very frequently, which brings unstable factors, especially when the CPU’s temperature is high. when

[0003] In another solution, the CPU only uses the clock source provided by the PLL with the highest frequency, and then the PLL is always locked at the highest frequency, and only the external frequency division value is modified during frequency modulation. In this solution, the OD frequency division value can only be 1, 2, Integer values ​​such as 4, 8, etc., this creates a huge gap in frequency

This will cause severe frequency fluctuations when the load is large but not full

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