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A SPI-based master-slave communication timing method

A technology of SPI module and SPI interface, which is applied in the direction of digital transmission system, instrument, transmission data organization to avoid errors, etc., and can solve the problems of low communication efficiency, no verification mechanism, short interval time, etc.

Active Publication Date: 2020-10-30
BEIJING CEC HUADA ELECTRONIC DESIGN CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] Defect 1: The entire communication process of SPI can only be controlled by the main SPI through the SS signal line, and the slave SPI has no active control right. This leads to the need to process corresponding commands and tasks after receiving data from the SPI, and the execution of each command by the slave SPI The time is different, which may lead to passive reception of unnecessary data from the SPI, thereby interfering with the current data receiving area, resulting in communication failure
[0006] In order to solve defect 1, some of the existing studies ensure the synchronization of master-slave communication by adding 4 signal handshake lines or 2 signal handshake lines. Although this type of research solves the problem of master-slave communication mismatch, it requires master Adding 2 or 4 hardware pins will bring hardware challenges and hardware costs;
[0007] In order to solve defect 1, some studies pointed out that after the main SPI sends the data, it starts to receive the data sent from the SPI through a fixed delay interval, but it is easy to cause either the interval time is too short, causing communication errors, or the interval time is too long, cause inefficiency in communication;
[0008] In order to solve defect 1, some studies have customized the SPI shift registers and receiving and sending buffers of both master and slave, but it will also bring hardware challenges and hardware costs, and is not universal
[0009] Defect 2: There is no verification mechanism and confirmation response mechanism in the SPI communication process, and there is no corresponding international standard or industry standard to avoid it. Therefore, when the communication environment is harsh, it is easy to be interfered by the outside world and cause communication failure.
[0010] In order to solve the second defect, the existing research has introduced a response mechanism through the formulation of a private communication protocol, using character transmission, that is, the sender transmits one byte, and the receiver confirms a fixed byte, but the protocol has the following three shortcomings: 1) Character transmission is used, and the communication efficiency is low; 2) There is no verification mechanism, if it is interfered by communication, it cannot be detected; 3) There is no error recovery mechanism, if the response byte is wrong, there is no retransmission mechanism to restore the communication link

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  • A SPI-based master-slave communication timing method
  • A SPI-based master-slave communication timing method
  • A SPI-based master-slave communication timing method

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Embodiment Construction

[0036] In order to make the above objects, features and advantages of the present invention more comprehensible, the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0037] One aspect of the present invention provides a master-slave communication timing method based on the SPI interface, such as figure 1 As shown, it mainly includes the following seven steps:

[0038] (1) After the main SPI sends 3 bytes of initial field data (PIB+LEN), the SS signal line fails (the SS signal is pulled high), and the failure time is 50us;

[0039](2) The active SS signal line of the main SPI sends subsequent data, and the data SS signal fails once every 16 bytes (the last time the main SPI sends data may be less than 16 bytes), and the failure time is 100us.

[0040] (3) After the main SPI sends the data, the SS signal is invalid for 100us;

[0041] (4) After receiving all the data from the SPI, clear the ha...

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Abstract

The invention discloses a master-slave communication system based on SPIs and a reliable transmission method based on the SPIs, and belongs to the technical field of communication. According to the scheme, on the one hand, a master-slave communication time sequence method based on the SPIs is provided, after salve SPI equipment closes an SPI module, an SS signal line of the master SPI is connectedwith a handshake line of the slave SPI, the handshake line can be multiplexed with an SS signal of the slave SPI and can also be a GPIO pin of the salve SPI equipment; on the other hand, the master-slave data reliable transmission method based on the SPIs is provided, a data link layer and an application layer are introduced, and the data link layer has an error retransmission processing mechanism. By means of the methods, the defects are overcome that communication time sequence matching of SPIs is difficult, and the communication reliability is low; the scheme is easy to implement, the hardware cost is low, the reliability is high, the transmission efficiency is high, and the compatibility is high.

Description

technical field [0001] The invention relates to the technical field of communication technology, in particular to an SPI-based master-slave communication system and a reliable transmission method. Background technique [0002] SPI (Serial Peripheral Interface), as the name implies, is a serial peripheral interface. The typical structure of the SPI bus is composed of four lines: SCLK, SS, MOSI and MISO. The SPI has two working modes: master mode and slave mode. The one that works in the master mode is the master SPI (that is, the master SPI device), otherwise it is the slave SPI (that is, the slave SPI device). [0003] SCK: serial clock line, used to synchronize the data transmission of the master-slave SPI device; SS: slave SPI chip select line, used to activate the slave SPI device, output by the master SPI, active low; MOSI: master SPI output slave SPI Input line, MISO: Master SPI input slave SPI output line. [0004] SPI, as a high-speed, full-duplex, synchronous comm...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F13/42H04L1/00
CPCG06F13/4286H04L1/0078
Inventor 伍延禄吕如茜崔海青
Owner BEIJING CEC HUADA ELECTRONIC DESIGN CO LTD
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