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Multi-phase non-overlapping clock signal generation circuit and corresponding method

A clock signal and generating circuit technology, applied in the direction of electrical pulse generator circuit, logic circuit to generate pulses, etc., can solve the problem of difficulty in designing multi-phase non-overlapping clock signals, etc.

Active Publication Date: 2021-11-05
PEKING UNIV SHENZHEN GRADUATE SCHOOL
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Thus, figure 1 It is difficult for the circuit to be used to realize the design of multi-phase non-overlapping clock signals

Method used

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  • Multi-phase non-overlapping clock signal generation circuit and corresponding method
  • Multi-phase non-overlapping clock signal generation circuit and corresponding method
  • Multi-phase non-overlapping clock signal generation circuit and corresponding method

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Embodiment Construction

[0027] Exemplary embodiments of the present application will be described in detail below with reference to the accompanying drawings. It should be noted that the relative arrangements of components and steps, numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present application unless specifically stated otherwise.

[0028] The following description of at least one exemplary embodiment is merely illustrative in nature and not intended as any limitation of the application, its application or uses.

[0029] Techniques, methods and devices known to those of ordinary skill in the relevant art may not be discussed in detail, but where appropriate, such techniques, methods and devices should be considered part of the description.

[0030] In all examples shown and discussed herein, any specific values ​​should be construed as exemplary only, and not as limitations. Therefore, other instances of the exemplary embodiment may ha...

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Abstract

The present application provides a clock signal generation circuit, including a clock signal generation unit configured to generate M original clock signals with the same pulse width, where M is an integer greater than or equal to 1; a control unit coupled to the clock signal generation unit , configured to periodically stimulate the clock signal generation unit to change the state of the original clock signal, and divide the effective level of each original clock signal into N parts, where N is an integer greater than or equal to 1; interval generation A unit, coupled to the clock generation unit, configured to process the M original clock signals, so that X parts of the active levels of each of the original clock signals are converted into inactive levels, and the converted A clock signal is provided to an output terminal of the circuit, where X is an integer greater than or equal to 1 and less than N. The present application also provides a corresponding method for generating multi-phase non-overlapping clocks.

Description

technical field [0001] The present application relates to the field of integrated circuits, in particular to a circuit for generating multi-phase non-overlapping clock signals and a corresponding method. Background technique [0002] The design of the clock signal is very important in many application fields. For example, in the field of power control, such as a charge pump circuit, the active levels of the clock signals that control the operation of different charge pump units should not overlap with each other, so as to reduce leakage and improve system work efficiency. For example, in the field of display, for example, in a shift register circuit, multi-phase non-overlapping clocks are also required to control the clock signals of shift register units at various levels, so as to realize progressive scanning. Setting the non-overlapping time can effectively avoid display errors caused by several lines being read at the same time. [0003] For two-phase clock applications...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03K3/027
CPCH03K3/027
Inventor 张敏林和生丁德东刘宾杰
Owner PEKING UNIV SHENZHEN GRADUATE SCHOOL
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