An Improved Method for Extracting Test Structure Parameters of Integrated Circuit Mosfet Transistors
A test structure and parameter extraction technology, which is applied in the direction of electrical digital data processing, CAD circuit design, special data processing applications, etc., can solve problems such as calculation errors, model accuracy reduction, and relatively large fluctuations in process parameters of integrated circuit products, and achieve improved The effect of manufacturing costs
Active Publication Date: 2021-06-29
JIANGSU MARINE RESOURCES DEV RES INST LIAN YUNGANG
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Problems solved by technology
[0029] Using the above de-embedding method has two main disadvantages. One is that a corresponding open circuit test structure and short circuit test structure need to be designed for each transistor, which obviously leads to relatively high costs; the other is that the process parameters of integrated circuit products fluctuate greatly. Even if the design structure is exactly the same, the extracted parameters of the test structure cannot be the same as the test structure parameters of the transistor itself, which will introduce calculation errors and reduce the accuracy of the model
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Embodiment 1
[0106] Embodiment 1: Based on the CMOS 130nm process, three multi-gate finger structure MOSFET transistors were produced, which are: M1, 0.13×5×8 (gate length×gate width×gate finger); M2, 0.13×5×16; M3, 0.13×5×32. First, measure the IV characteristics and S parameter characteristics of the transistor based on the network analyzer and semiconductor parameter analyzer, and then extract the parameters based on the steps given above. The final extraction results are shown in the following table:
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[0109] Figure 9 A comparison chart of the measured and simulated S-parameters of the open-circuit and short-circuit test structures is given, with a maximum frequency of 40 GHz. Figure 10 and Figure 11 The simulation and test S-parameter comparison charts of MOSFET transistors are given. The dimensions of the transistors are 130×5×8 and 130×5×16 respectively. From the figure, it can be seen that the simulation and test parameters are consistent, and they mat...
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The invention discloses an improved technique for extracting parameters of the test structure of an integrated circuit MOSFET transistor. When designing the MOSFET transistor to be tested using the technology of the invention, it is necessary to design and manufacture an open circuit test structure and a short circuit test structure. Through these two special The test structure enables the extraction of parasitic parameters of the test structure. However, the additional open-circuit test structure and short-circuit test structure occupy a dedicated chip area, which increases the cost of chip manufacturing.
Description
technical field [0001] The invention relates to a transistor detection technology, in particular to an improved method for extracting test structure parameters of an integrated circuit MOSFET transistor. Background technique [0002] The designed integrated circuit schematic diagram needs to be simulated to confirm that the circuit output results meet the design requirements. In order to ensure that the simulation results are as consistent as possible with the actual measurement results, an accurate MOSFET transistor model must be established. When the IV characteristics and S parameters of the device are directly measured on the wafer, since the size of the MOSFET device on the chip is very small, it cannot be directly contacted. It is necessary to design a test structure (Test Structure) so that the Coplanar Probe (Coplanar Probe) can be used. ) to measure its RF characteristics. The test structure usually consists of a probe pad (Probe Pad), a metal interconnecting line ...
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IPC IPC(8): G06F30/3308
CPCG06F30/30G06F30/367
Inventor 程加力胡全斌董自健
Owner JIANGSU MARINE RESOURCES DEV RES INST LIAN YUNGANG