Chip package structure

Abstract

The invention discloses a chip package structure. The chip package structure comprises a chip, a first circuit board, an insulation layer and a second circuit board, wherein an acting region and a plurality of crystal cushions are arranged on a front surface of the chip, the plurality of crystal cushions are arranged at least one side edge of the acting region, a plurality of first circuit layersare arranged on a first surface of the first circuit board and are respectively and correspondingly connected with the crystal cushions arranged on the front surface of the chip, the insulation layeris covered on the first surface of the first circuit board and a back surface of the chip, the second circuit board is provided with a first surface and a second surface, the first surface is coveredon a back surface of the insulation layer, a plurality of second circuit layers are arranged on the second surface and are used for correspondingly connecting to an external printed circuit board, each first circuit layer arranged on the first circuit board and each second circuit layer arranged on the second circuit board are correspondingly and electrically connected via a conductive penetratinghole, and each conductive penetrating hole is arranged outside a surrounding part of the chip and penetrates through the first circuit board, the insulation layer and the second circuit board.

Description

technical field [0001] The present invention relates to a package structure of a chip, in particular to a chip with a plurality of conductive through holes (PTH, Plated Through Hole) arranged on the outside, so that each crystal pad provided on the front side of the chip can pass through the chip. A plurality of conductive through holes (PTH) are moved to the back of the fingerprint identification chip to be electrically connected and installed on a printed circuit board, so that the active area set on the front of the chip can cooperate with the printed circuit board to achieve Function of the area of ​​action. Background technique [0002] Using surface mount technology (SMT) to electrically connect a chip in a flip-chip manner and mount it on a printed circuit board (PCB) is a common configuration and existing technology for chips at present. At this time, the chip A plurality of die pads set on the front face of the printed circuit board (PCB) face the printed circuit b...

AI Technical Summary

Problems solved by technology

Since the active area (fingerprint recognition sensing area) 13 is external induction, its surface must face the opposite side of the printed circuit board (60), otherwise it will be covered by the printed circuit board, so the front surface 11 of the chip 10 A plurality of crystal pads 14 cannot be electrically connected and installed on the printed circuit board (60) in a flip-chip manner

[0004] Although other bonding methods can be used for electrical connection between the plurality of crystal pads 14 on the front side 11 of the chip (fingerprint recognition chip) 10 and the printed circuit board, such as wire bond, the used The wire is pulled from the surface of the crystal pad 14 in an arc shape to the printed circuit board located at the back side 12 of the chip 10, so the highest point of the wire is relatively higher than the front side 11 of the chip 10 or the crystal pad 14 on it by a certain height , and an insulating outer sheath is generally provided on the periphery of the plurality of wires (wires) to cover and protect these wires (wires), resulting in a relative increase in the overall height of the package structure of the chip after fabrication. Does not meet the requirements of thin and short

In addition, a plurality of through-silicon vias (TSV, Through Silicon Via) for electrical conduction are arranged between the front side 11 and the back side 12 of the chip 10. This type of through-silicon via (TSV) design is commonly used in chip packaging and related existing technologies. In technology, but the manufacturing process is relatively cumbersome and complicated, not in line with economic benefits

[0005] As can be seen from the above, for a chip that is provided with a plurality of crystal pads 14 and an active area (such as a fingerprint identification sensing area) on the front side at the same time, the structure and / or manufacturing process of the prior art in the art can be realized. It is difficult to meet the needs of actual use, so in the field of packaging of such chips, there is still a need for further improvement

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