Construction method of symbol synchronization circuit in bluetooth edr receiver

Abstract

The invention provides a construction method for a symbol synchronization circuit in a Bluetooth EDR receiver. The method comprises the following steps that interpolation calculation is conducted on aBluetooth EDR baseband signal; timing error information detection is conducted on the basis of interpolation calculation; timing error information is filtered by a loop filter, data obtained after filtering is output to a numerically-controlled oscillator for an accumulation operation, and then corresponding interpolation coefficients are calculated out; and detection of a DPSK synchronization head is conducted on the output of a symbol synchronization module by means of 11 known DPSK signals, and after the synchronization head is detected, symbol data recovered by an interpolator is sent toa next-stage differential demodulation and frequency offset compensation circuit.

Description

technical field [0001] The invention relates to the field of fast symbol synchronization in a bluetooth receiver, in particular to a method for constructing a symbol synchronization circuit in a bluetooth EDR receiver. Background technique [0002] Signals received by wireless digital receivers often have symbol timing deviations during communication. Therefore, it is necessary to restore the best sampling point through a symbol synchronization circuit. The all-digital receiver adopts a fixed sampling frequency, the sampling clock and the symbol clock are independent of each other, and the timing error obtained by the timing synchronization circuit is used to control the interpolation filter, so that it can restore the original symbol value at the optimal sampling point. [0003] Generally speaking, the symbol synchronization circuit is composed of four parts including an interpolation filter (Interpolator), a timing error detector (CTimingError Detector), a loop filter (LP...

AI Technical Summary

Problems solved by technology

Among them, the sooner or later gate algorithm works at 3 times the symbol rate, so the hardware overhead is large; the MM algorithm works at 1 times the symbol rate, but requires the carrier phase synchronization to be completed first; the Gardner algorithm works at 2 times the symbol rate, and it has a carrier frequency offset. The situation is also normal, but its synchronization speed is greatly affected by the roll-off factor of the raised cosine filter

Images