Signal synchronization control method and apparatus

Abstract

The invention provides a signal synchronization control method and apparatus. The signal synchronization control method comprises the following steps: collecting digital logic signals and synchronousclock signals corresponding to the digital logic signals, judging whether the digital logic signals have a resonance phenomenon, and when the digital logic signals have the resonance phenomenon, adjusting the duty ratios of the digital logic signals and the synchronous clock signals according to a preset reference clock to eliminate the resonance phenomenon. By changing the duty ratios of the digital logic signals and the synchronous clock signals, the resonance phenomenon between the digital logic signals is eliminated, the number of the digital logic signals that jump to the falling edge under the triggering on the rising edge of the respective synchronous clock signals can be reduced, and the "resonance" phenomenon is reduced, thereby reducing the electromagnetic interference to an MCUand improving the stability of the system.

Description

technical field [0001] The invention relates to the technical field of digital signal processing, in particular to a signal synchronization control method and device. Background technique [0002] The synchronization design of each digital logic signal is the most important content in the design of the digital logic control of the current micro control unit (Micro Controller Unit, referred to as MCU). In general, each digital logic signal can be controlled synchronously through a clock domain. Specifically, a unique fixed frequency is set for the clock domain, and all digital logic signals jump based on the rising edge or falling edge of the clock domain. For example, set on a rising edge, or release on a falling edge. [0003] In an MCU with complex digital logic control, a large number of digital logic signals are often required. When the frequency of the synchronous clock is extremely high, it often occurs that a large number of digital logic signals jump to the rising...

AI Technical Summary

Problems solved by technology

When the frequency of the synchronous clock is extremely high, it often occurs that a large number of digital logic signals jump to the rising edge of the corresponding clock control signal at the same time, and the probability of jumping to the falling edge at the same time also increases significantly, and the above digital logic signals simultaneously jump to The phenomenon of falling edge may cause "resonance" phenomenon

In practical applications, when the above-mentioned "resonance" phenomenon occurs, the power consumption of the internal current of the MCU will increase rapidly. When the current changes instantaneously at a high frequency, it may cause large electromagnetic interference to the entire MCU, resulting in system instability.

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