A kind of emmc test method and device
A test method and lower computer technology, applied in static memory, instruments, etc., can solve the problems of low test efficiency, improve test efficiency and avoid data packet loss
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Embodiment 1
[0020] figure 1 A schematic flow diagram of an eMMC testing method provided in Embodiment 1 of the present invention, the method is applicable to the situation of eMMC testing, and can be executed by an eMMC testing device, wherein the device can be implemented by software and / or hardware, and can generally be integrated in the eMMC testing platform. Such as figure 1 As shown, the method includes the following steps:
[0021] Step 110, if the lower computer detects that it has received the message, the lower computer is in the interrupt state, and the state of the corresponding USB endpoint is in an unreceivable state.
[0022] Typically, the eMMC test development platform is usually composed of a host computer and a lower computer. The upper computer refers to a computer that can directly issue control commands, and the lower computer is a computer that directly controls the device to obtain the status of the device. The command issued by the upper computer is first given t...
Embodiment 2
[0030] figure 2 A schematic flow diagram of an eMMC testing method provided by Embodiment 2 of the present invention. On the basis of the above embodiments, this embodiment optimizes the "response message of the lower computer according to the determination result", such as figure 2 As shown, the method includes the following steps:
[0031] Enter step 210 after the eMMC test starts.
[0032] Step 210, the lower computer detects whether it has received the message, if not, execute step 220, and if yes, execute step 230.
[0033] Step 220, enter the main loop.
[0034] Exemplarily, the technical solution provided in this embodiment is only an exemplary description of a certain performance test, such as eMMC write test, and entering the main loop may be to execute other test commands in the eMMC test platform, such as read test.
[0035] Step 230, the lower computer is in an interrupted state, and the state of the corresponding USB endpoint is in an unacceptable state.
[...
Embodiment 3
[0049] image 3 It is a schematic structural diagram of an eMMC testing device provided in Embodiment 3 of the present invention. The device can be implemented by software and / or hardware, and can perform eMMC testing by executing an eMMC testing method. Such as image 3 As shown, the device may include:
[0050] The message detection module 310 is used for if the lower computer detects that it receives a message, the lower computer is in an interrupt state, and the state of the corresponding USB endpoint is in an unreceivable state;
[0051] The data detection module 320 is used for the lower computer to determine whether the data type command is included in the message;
[0052] The response module 330 is used for the lower computer to respond to the message according to the determination result.
[0053] In the technical solution provided by this embodiment, if the lower computer detects that it has received a message, the lower computer automatically enters the interrup...
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