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HEVC decoding method based on multi-core platform multi-level task-level and data-level parallelism

A decoding method and multi-layer technology, applied in the field of HEVC decoding, can solve the problems of insufficient utilization of multi-core resources, insufficient consideration of dependencies, and increased delay, and achieve the effect of improving the utilization of multi-core resources

Active Publication Date: 2018-08-24
NANJING UNIV OF POSTS & TELECOMM
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  • Abstract
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  • Claims
  • Application Information

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Problems solved by technology

However, their research has certain limitations. For example, when processing each task module in parallel, the parallel granularity is based on the CTU behavior. The decoder uses a single thread to serially decode a row of CTUs, but the pixel decoding module and the deblocking filter module. The dependency relationship during parallel processing exists on each CTU unit, not the CTU row, which will increase the delay to a certain extent, and at the same time make the multi-core resources cannot be fully utilized, resulting in a waste of core resources
In addition, the parallel processing of the deblocking filter completely separates the filtering operations of the vertical boundary and the horizontal boundary, does not fully consider the dependencies of each boundary, and fails to combine the filtering operations of the vertical boundary and the horizontal boundary to achieve parallel operation. Parallel efficiency has not been effectively improved

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  • HEVC decoding method based on multi-core platform multi-level task-level and data-level parallelism
  • HEVC decoding method based on multi-core platform multi-level task-level and data-level parallelism
  • HEVC decoding method based on multi-core platform multi-level task-level and data-level parallelism

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Embodiment Construction

[0030] The present invention will be further described below in conjunction with the accompanying drawings. The following examples are only used to illustrate the technical solution of the present invention more clearly, but not to limit the protection scope of the present invention.

[0031] The present invention adopts Tilera GX36 multi-core processor as a hardware experiment platform, which is composed of 36 Tile cores. The Tilera multi-core processor has a complete set of multi-core development tools, which provides convenience for the development of multi-core parallel programs.

[0032] figure 1 The flowchart of the method embodiment of the present invention; Specifically follow the steps below:

[0033] First step 1, the main thread first initializes the entire decoder, reads the binary stream file, creates the HEVC decoder and applies for the memory unit;

[0034] Further, in step 2, intercept the code stream of the current frame from the read binary code stream and ...

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Abstract

The invention discloses an HEVC decoding method based on multi-core platform multi-level task-level and data-level parallelism. According to the method, the dependency in HEVC data is utilized, a multi-core processor serves as a processing platform, and an HEVC standard is combined, so that the whole HEVC decoder is divided into five task modules, which is composed of a code stream reading module,an entropy decoding module, a pixel reconstruction module, a deblocking filtering module and a sample point adaptive compensation module; a parallel method is designed for different decoding task modules respectively; meanwhile, an assembly line parallel processing of the different decoding tasks based on a CTU unit is realized between the modules through the dependence relation of the CTU units.A data redundancy reduction mechanism is introduced, and only partial reference pixel points are placed in a cache space, so as to avoid excessive data operation; the buffer storage space is effectively managed, and the decoding efficiency is improved. Compared with serial decoding, the multi-core parallel decoding algorithm adopted by the method greatly improves the parallel acceleration ratio of decoding, and the quality of the decoded image is ensured.

Description

technical field [0001] The invention belongs to the field of encoding and decoding of digital video signals, and in particular relates to an HEVC decoding method based on multi-level task levels and data levels in parallel on a multi-core platform. Background technique [0002] With the rapid increase of high-definition and ultra-high-definition video applications, in order to improve the compression performance and meet the transmission and storage requirements of massive video data, the video coding joint collaboration group JCT-VC officially released a new generation of high-efficiency video codec international standards in April 2013. Standard HEVC (High Efficiency Video Coding). The main goal of the HEVC codec standard is to double the compression efficiency of high-resolution video images and reduce the bit rate of video streams by 50% on the basis of the H.264 / AVC standard while ensuring the same video image quality. %, so as to better adapt to various network enviro...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04N19/44H04N19/436H04N19/176H04N19/70H04N19/42H04N19/82H04N19/86H04N19/96H04N19/124H04N19/117H04N19/13H04N19/91
CPCH04N19/117H04N19/124H04N19/13H04N19/176H04N19/42H04N19/436H04N19/44H04N19/70H04N19/82H04N19/86H04N19/91H04N19/96
Inventor 胡栋韩峰谷涛
Owner NANJING UNIV OF POSTS & TELECOMM