A kind of gan HEMT device and preparation method thereof
A device, N-type technology, applied in the field of GaN HEMT devices and their preparation, can solve the problems of limiting the high-frequency characteristics of GaN HEMT devices, increasing the complexity of the preparation process of the device, and large source-drain parasitic resistance, so as to reduce parasitic capacitance and narrow the gate. The effect of long dimensions, excellent RF characteristics
- Summary
- Abstract
- Description
- Claims
- Application Information
AI Technical Summary
Problems solved by technology
Method used
Image
Examples
Embodiment 1
[0040] This embodiment provides a GaN HEMT device. refer to figure 1 As shown, the GaN HEMT device includes a substrate 1, a buffer layer 2, a GaN channel layer 3, a barrier layer 4, an N-type cap layer 5, a first passivation layer 6, a first dielectric layer 7, a second passivation layer A metallization layer 8 , a second dielectric layer 9 , a gate metal layer 10 and a source-drain metal layer 11 .
[0041]The buffer layer 2 is stacked on the substrate 1; the GaN channel layer 3 is stacked on the buffer layer 2; the barrier layer 4 is stacked on the GaN channel layer 3; the N-type cap layer 5 is stacked on the barrier layer 4; the source-drain metal layer 11 is stacked on the outer edge of the N-type cap layer 5, the first A passivation layer 6 is also stacked on the N-type cap layer 5, the first dielectric layer 7 is stacked on the first passivation layer 6, the first passivation layer 6 and the The first dielectric layer 7 is located between the source-drain metal layer...
Embodiment 2
[0055] This embodiment provides a preparation method of a GaN HEMT device, comprising the following steps:
[0056] S1, sequentially epitaxially form a buffer layer 2, a channel layer 3, a barrier layer 4 and an N-type cap layer 5 on the substrate 1, such as figure 2 shown;
[0057] S2, sequentially depositing the first passivation layer 6 and the first dielectric layer 7 on the N-type cap layer 5, and selectively removing part of the first passivation layer, part of the first dielectric layer and part of the N-type cap layer by dry etching A cap layer is formed, thereby forming a gate metal region 12 penetrating the middle of the first dielectric layer 7, the first passivation layer 6 and the N-type cap layer 5, such as image 3 and 4 shown;
[0058] S3, sequentially depositing the second passivation layer 8 and the second dielectric layer 9, and performing dry etching on the second passivation layer 8 and the second dielectric layer 9 to make the upper surface of the bar...
PUM
| Property | Measurement | Unit |
|---|---|---|
| width | aaaaa | aaaaa |
| width | aaaaa | aaaaa |
| thickness | aaaaa | aaaaa |
Abstract
Description
Claims
Application Information
Login to View More 


