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Method and device for abnormal power-down data protection of non-volatile memory

A non-volatile memory and electrical data technology, applied in the direction of electrical digital data processing, data processing power supply, data processing input/output process, etc., can solve the problem of blank, on-board memory density limit, super capacitor power limit, etc. question

Inactive Publication Date: 2018-09-04
ZHENGZHOU YUNHAI INFORMATION TECH CO LTD
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  • Summary
  • Abstract
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  • Claims
  • Application Information

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Problems solved by technology

[0003] In the X86 field, the existing technical solutions are mainly monopolized by foreign manufacturers, using the non-volatile memory sticks of foreign manufacturers plus a super capacitor solution. When an abnormal power failure occurs, the external super capacitor starts to be a non-volatile memory stick, which can realize Electronic data protection, but the domestic technology is still blank
In addition, the solution of using a non-volatile memory module plus a super capacitor is currently in the verification stage. Due to the limited power of the super capacitor, generally speaking, a non-volatile memory needs to be equipped with a super capacitor, which sacrifices the limited capacity of the board to a certain extent. space, there are great restrictions on the density of on-board memory, and the structural design will also face great challenges

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  • Method and device for abnormal power-down data protection of non-volatile memory
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  • Method and device for abnormal power-down data protection of non-volatile memory

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Embodiment Construction

[0037] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described The embodiments are only some of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts shall fall within the protection scope of the present invention. In order to enable those skilled in the art to better understand the technical solutions in the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described The emb...

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Abstract

The present invention provides a method and device for abnormal power-down data protection of a non-volatile memory. The method comprises steps of detecting whether or not an abnormality occurs in a power signal of a PSU; when an abnormality occurring in the power signal of the PSU, switching BBU to supply power, and simultaneously sending a configuration command before shutdown; when it is detected that the configuration is completed before the shutdown, sending a power-off command to turn off other power source units, and sending an instruction to store cache data in the non-volatile memory;on the basis of the non-volatile memory, a battery backup unit is added to ensure that the cached data is stored in the non-volatile memory in time under an abnormal power-down condition to prevent data loss, which fills the blank in related technical fields in China, and a super capacitor is not added to affect board card space and memory density.

Description

technical field [0001] The invention relates to the technical field of computer storage, in particular to a data protection method and device for abnormal power failure of non-volatile memory. Background technique [0002] Non-volatile memory is one of the new directions of server design exploration at present. Different from conventional DDR DRAM, the data of non-volatile memory can be completely stored in memory after power failure. The current non-volatile memory mostly uses Flash as the storage medium. Since the read and write speed of Flash is much slower than the response speed of the memory controller, a first-level cache is generally added between the memory controller and the non-volatile memory to alleviate the two problems. Due to the difference in speed, the data interacts between the memory controller and the non-volatile memory through the cache, which not only has data non-volatility, but also takes into account the performance of data reading and writing. Si...

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Application Information

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IPC IPC(8): G06F1/30G06F3/06
CPCG06F1/30G06F3/0619G06F3/0679
Inventor 周亮
Owner ZHENGZHOU YUNHAI INFORMATION TECH CO LTD
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