LDO voltage stabilizer circuit without off-chip capacitor

Abstract

The invention discloses an LDO voltage stabilizer circuit without an off-chip capacitor. The LDO voltage stabilizer circuit is applied to an on-chip system. When the output voltage of an output modulerushes up or down, a grid of a power adjusting tube can be charged and discharged by a charging module and a discharging module so as to enhance the transient response; if the output voltage does notrush to the reference voltage output by a reference module when rushing down, a switch capacitor circuit can be closed so as to increase the grid capacitance of the power adjusting tube, and the effects of reducing the hopping speed of the output voltage and reducing the further rushing-down of the output voltage are realized; after the output voltage rushes down to the reference voltage, the switch capacitor circuit can be opened so as to enhance the grid voltage slew rate of the power adjusting tube, and the effects of shortening the establishing time after the transient response and accelerating the steady state restoration of the system are achieved. It can be seen that the restraining relation of restraining the output voltage hopping and shortening the establishing time after the transient response can be eliminated by means of the LDO voltage stabilizer circuit.

Description

technical field [0001] The invention relates to the field of circuits, in particular to an LDO regulator circuit without external capacitors. Background technique [0002] Integration is one of the development trends in the semiconductor industry. Circuit modules with various functions will become increasingly miniaturized and high-frequency, and finally integrated into a system-on-chip (SOC). Among them, the LDO voltage regulator (low-voltage linear voltage regulator) is used to provide high-precision voltage for each circuit module of the SOC, and its performance directly affects the performance of the SOC. Since the LDO regulator without off-chip capacitor has the advantages of small size and few external interfaces, it is easy to integrate. Therefore, at present, most of the research on the on-chip integrated LDO regulator is based on the LDO regulator without off-chip capacitor. device. [0003] In the prior art, in order to improve the frequency characteristics and t...

AI Technical Summary

Problems solved by technology

However, although the solution of adding a buffer on the main road can improve the instantaneous dynamic response characteristics, it will not only increase the static power consumption, reduce the efficiency of the LDO regulator, but also affect the frequency response. When the load changes suddenly, the output of the LDO regulator The voltage jump is severe and the stability is poor; while the scheme of increasing the gate-drain capacitance of the power adjustment tube can improve the frequency characteristics, it will not only prolong the settling time after the transient response (from the output voltage upshoot to the highest or undershoot to the minimum until the output voltage returns to the steady-state value), the instantaneous dynamic response performance is poor, and the layout area will be increased, which will increase the difficulty of integration

It can be seen that the existing technical solutions for improving the instantaneous dynamic response characteristics of the LDO voltage regulator are difficult to suppress the jump of the output voltage of the LDO voltage regulator, and the frequency characteristics are poor; the existing technical solutions for improving the frequency characteristics of the LDO voltage regulator , the settling time after the transient response is prolonged, and the transient dynamic response characteristics are poor

That is to say, in the existing technical solutions, there is a restrictive relationship between suppressing the output voltage jump of the LDO regulator and shortening the settling time after the transient response

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