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Double-chip packaging structure

A packaging structure, two-chip technology, applied in the direction of semiconductor/solid-state device components, semiconductor devices, electrical components, etc., can solve the problems of increasing the manufacturing cost and increasing the size of the chip package, avoiding equipment conflicts, low manufacturing costs, and leading The effect of a small number of feet

Inactive Publication Date: 2018-09-07
LYONTEK
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

read on figure 2 , in order to avoid device conflicts between different SPI memory chips in the same package structure, in the double-chip package structure of the known SPI memory chip 420, in addition to having a GND pin 422, the SPI memory chip 420 also includes two The CS pins 421a and 421b (i.e. CS1 and CS2) are used to distinguish the control signals of two different SPI memory chips in the package structure. Therefore, the double-chip package structure of this type of SPI memory chip 420 needs to set ten pins (including An empty pin NC), will undoubtedly increase the package size of the chip, and will increase its manufacturing cost

Method used

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Embodiment Construction

[0067] The following content will be combined with drawings to illustrate the technical content of the present invention through specific specific embodiments. Those familiar with this technology can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied by other different specific embodiments. Various details in this specification can also be modified and changed based on different viewpoints and applications without departing from the spirit of the present invention. In particular, the proportional relationship and relative positions of the various components in the drawings are merely exemplary and do not represent the actual implementation of the present invention.

[0068] Please refer to Figure 3A and Figure 3B with Figure 3C ,among them Figure 3A Is a side view of the dual-chip package structure 100 of the first embodiment of the present invention...

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Abstract

The invention provides a double-chip packaging structure. An exposed pad is arranged and serves as a grounding end, GND wiring pads of two chips in the packaging structure are electrically connected to the exposed pad, a lead frame includes two CS pins electrically connected to CS wiring pads respectively, and thus, on the premise that the packaging structure includes eight pins, equipment conflict between the two chips is avoided. The double-chip packing structure with fewer pins can reduce the cost effectively.

Description

Technical field [0001] The present invention relates to a semiconductor package, and more specifically, to a two-chip package structure. Background technique [0002] As the application of micro and small electronic devices becomes more and more common (such as wearable electronic devices), low-pin-count packages and multi-storage chips have the advantages of smaller product sizes and lower manufacturing costs, which are also in the market. It is becoming more and more popular, for example, serial peripheral interface flash memory (SPI Flash) and static random access memory (SPI SRAM). In addition, the eight-pin package structure is currently the most economical and smallest package structure in terms of manufacturing cost. [0003] MCP (Multi Chip Package) is an extension of the new technology of semiconductor system-in-package and multi-chip packaging. It is designed to stack a variety of chips including NOR Flash, NAND Flash, Low Power SRAM and PseudoSRAM into 1 A MCP chip (su...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L25/065H01L23/495
CPCH01L23/49575H01L25/0657H01L23/4952H01L2924/181H01L2224/32145H01L2224/48091H01L2224/48247H01L2224/73265H01L2924/00014H01L2924/00012H01L2924/00
Inventor 洪奇正黄鹏如
Owner LYONTEK
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