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An Out-of-Sequence and Calibration Method for Non-Loop-Structured Sar ADC

A calibration method, a non-loop technology, applied in the direction of analog/digital conversion calibration/test, code conversion, electrical components, etc., can solve the problems of multiple comparator calibration effects, comparator offset, comparator mismatch, etc., to save Effect of hardware consumption, SFDR improvement, and reduction of stabilization time

Active Publication Date: 2021-06-01
SOUTHEAST UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] The technical problem to be solved by the present invention is to overcome the deficiencies of the prior art, provide a disorder and calibration method suitable for non-loop structure SAR ADC, and solve the problem that the introduction of multiple comparators will cause comparator imbalance and Mismatch between, making the calibration of multiple comparators affected

Method used

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  • An Out-of-Sequence and Calibration Method for Non-Loop-Structured Sar ADC
  • An Out-of-Sequence and Calibration Method for Non-Loop-Structured Sar ADC
  • An Out-of-Sequence and Calibration Method for Non-Loop-Structured Sar ADC

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Embodiment Construction

[0031] Embodiments of the present invention will be described below in conjunction with the accompanying drawings.

[0032] Such as figure 1 Shown is the overall structural frame diagram of the calibration method of the present invention applied to 8bit SAR ADC, including 9 comparators COMP1~COMP9, a reference comparator REFCOMP, and out-of-sequence and calibration control logic.

[0033] Nine of the comparators and the reference comparator are used as figure 2 The structure shown specifically includes MP1a, MP1b, MP2a, MP2b, MN1, MN2a, MN2b, MN3a, MN3b, MN4a, and MN4b, wherein MP1a, MP1b, MP2a, and MP2b are PMOS tubes, and MN1, MN2a, MN2b, MN3a, MN3b , MN4a and MN4b are NMOS tubes.

[0034] Such as figure 2 In the shown circuit structure, the source of MP1a is connected to the source of MP1b, the source of MP2a and the source of MP2b, and its connection point is connected to the power supply VDD; the gate of MP1a is connected to the drain of MP2b, the drain of MN4a The ...

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Abstract

The invention discloses a disorder and calibration method applicable to a SAR ADC with a non-loop structure. According to the comparison result, the voltage value is increased to compensate for the offset; in each conversion cycle, the comparator is operated out of order, and a pseudo-random number sequence is used to select one to compare the MSB bit of the second conversion; for the comparator after the out-of-order operation Carry out calibration, including: judging whether the current comparison cycle is LSB bit comparison, and when judging as LSB bit comparison, comparing the output results of the reference comparator and LSB bit comparator, and increasing the calibration of the LSB bit comparator input according to the comparison result Voltage. The present invention calibrates by comparing the output results of the disordered LSB bit comparator and the fixed reference comparator, without adding extra time and speeding up the convergence speed of the calibration algorithm.

Description

technical field [0001] The invention relates to a random sequence and calibration method suitable for non-loop structure SAR ADC, belonging to the technical field of SAR ADC. Background technique [0002] High-speed and low-power analog-to-digital converters are widely used in the communication field. Traditional SAR ADCs are limited by their working principles, making it difficult to achieve high-speed performance. In recent years, with the continuous development of advanced technology, SAR ADC has benefited from its high degree of digitality, and its speed can be relatively high. Many studies have devoted themselves to greatly increasing the speed of SAR ADC through structural improvements. Among them, the non-loop structure uses a separate comparator to work in each comparison cycle, which greatly reduces the logic delay of the traditional loop structure and improves the conversion speed. However, the introduction of multiple comparators will cause the offset of the comp...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03M1/10
CPCH03M1/1009
Inventor 吴建辉包天罡孙杰李红王鹏王甫锋
Owner SOUTHEAST UNIV
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