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PCS (Physical Coding Sublayer) protocol reuse chip and method

A protocol and chip technology, applied in the field of PCS protocol multiplexing chips, can solve the problems of waste of logic resources and high cost of chip usage, and achieve the effect of reducing usage costs and saving logic resources.

Inactive Publication Date: 2018-09-14
TIANJIN CHIP SEA INNOVATION TECH CO LTD +1
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  • Abstract
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  • Claims
  • Application Information

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Problems solved by technology

[0005] In view of this, the purpose of the present invention is to provide a PCS protocol multiplexing chip and method, to alleviate the technical problems of waste of logic resources and high cost of chip use in the prior art

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  • PCS (Physical Coding Sublayer) protocol reuse chip and method
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  • PCS (Physical Coding Sublayer) protocol reuse chip and method

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Embodiment Construction

[0053] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present invention, not all of them. the embodiment. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

[0054] At present, under the same architecture, only the transmission of data at the 10G backplane Ethernet physical coding sublayer or the 10.3125G high-speed serial physical coding sublayer can be realized separately, which takes up a lot of logic resources and increases the cost of using the chip. Based on this , a PCS protocol multiplexing chip and method provided by the embodime...

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Abstract

The invention provides a PCS (Physical Coding Sublayer) protocol reuse chip and method. The chip comprises a first encoding module for encoding sending data in a sending passageway; a second encodingmodule for encoding the sending data in the sending passageway; and an encoding selection module for receiving a first enabling signal transmitted by a first enabling signal wire and encoding the sending data by using the first encoding module or at the second encoding module under the control of the first enabling signal. The embodiment of the invention can realize transmission of data packaged according to a 10 GBase-KR PCS protocol and a 10.3125 GSerial RapidIO PCS protocol under the same architecture, so that a large number of logic resources are saved, and the use cost of the chip is reduced.

Description

technical field [0001] The invention relates to the technical field of computer software, in particular to a PCS protocol multiplexing chip and method. Background technique [0002] Ethernet is a computer local area network based on data frame transmission. With the continuous development of Ethernet technology, the application of Ethernet technology has expanded from the initial local area network to metropolitan area network and wide area network, and its application range is extremely wide. [0003] High-speed serial (RapidIO) technology is mainly for the interconnection communication of high-performance embedded systems, which has higher transmission efficiency than Ethernet, and because RapidIO technology has relatively complete considerations in routing, switching, error tolerance and error correction, and ease of use , which can realize high-performance and reliable data transmission based on hardware. [0004] Both Ethernet and RapidIO are widely used protocols. In...

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Application Information

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IPC IPC(8): H04L29/06
CPCH04L69/18
Inventor 刘长江刘勤让宋克朱珂沈剑良吕平杨镇西陶常勇汪欣李沛杰黄雅静杨堃付豪张楠陈艇何丽丽
Owner TIANJIN CHIP SEA INNOVATION TECH CO LTD
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