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a hardware accelerator

A hardware accelerator and accelerator technology, applied in the field of circuits, can solve the problems of poor portability of hardware accelerators, many hardware accelerator components, waste of system cache, etc., and achieve the effect of achieving light weight, reducing the number of components, and enriching the cache structure.

Active Publication Date: 2022-05-17
ALLWINNER TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] In view of this, the embodiment of the present invention provides a hardware accelerator to solve the problems in the prior art that the hardware accelerator has poor portability, occupies and wastes a large amount of system cache, and has many hardware accelerator components, high power consumption, and low battery life.

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Experimental program
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Embodiment 1

[0084] figure 1 A structural diagram of a hardware accelerator provided by Embodiment 1 of the present invention. The hardware accelerator of this embodiment specifically includes:

[0085] An acquisition unit (110), the acquired image data includes a left view and a right view.

[0086] In this implementation, the left side view and the right side view specifically refer to two images including the same target object obtained from two different positions, specifically, they can be obtained through two identical or different cameras at different positions The left view and the right view may also be obtained by moving the same camera, which is not limited in this embodiment.

[0087] Wherein, the target object specifically refers to an object included in the ROI of the left view. It can be understood that when two images are generally matched, the image area of ​​the important object in one image is mainly matched with the whole or part of the image area of ​​the other imag...

Embodiment 2

[0098] Figure 4 It is a schematic diagram of a search block generated by a control unit provided in Embodiment 2 of the present invention.

[0099] The control unit (160) sets a search block respectively in the left view and the right view, which are respectively the left view search block (1601) and the right view search block (1602), and the search block slides horizontally in the view to search Every time the center of the block slides to a position, it can cover the pixels of the size of the search block. The left view search block (1601) and the right view search block (1602) are both square search blocks with the size of winsize*winsize, so The above winsize is an odd number, and 5≤winsize≤21.

[0100] Such as Figure 4 As shown, the center of the search block (1601) slides horizontally to the right in the A-th pixel row in the region of interest of the left view, and the center of the search block (1602) slides horizontally to the left in the corresponding pixel row ...

Embodiment 3

[0110] Figure 5 It is a working schematic diagram of the first operation subunit (1301) provided by Embodiment 3 of the present invention.

[0111] Such as Figure 5 As shown, the first operation subunit (1301) includes a plurality of subtractors and adders, and the first operation unit (1301) is connected to the logic bank group (120) for calculating the initialization operation corresponding HSAD, the first computing subunit (1301) is also connected to the information warehouse (140), and sends the calculation result to the information warehouse (140);

[0112] The calculation method of the HSAD corresponding to the initialization operation is described in detail below:

[0113] In this embodiment, when the center of the search block in the left view slides to the A-th pixel row of the region of interest in the left view for the first time, the control unit sends a control signal to the computing unit, and the computing unit performs an initialization operation. The init...

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Abstract

The invention discloses a hardware accelerator for improving CPU operating efficiency. The hardware accelerator includes a storage unit, a logic bank group, an information warehouse, a bilateral operation unit, a comparison unit and a control unit. On the basis of the prior art, the hardware accelerator protected by the present invention replaces the software algorithm to give full play to the inherent processing speed advantages of the hardware, and sets a logic bank group composed of block logic banks, which can provide rich cache space options and avoid The waste of cache resources, by setting information bins and bilateral computing units, improves the point-based operations in the traditional image processing process to row-based operations, and uses the calculation results of the previous position to iteratively calculate the results of subsequent positions, greatly reducing hardware accelerators. The number of components required in the system realizes lightweight hardware structure.

Description

technical field [0001] This application relates to the field of circuits, more specifically a hardware accelerator. Background technique [0002] Computer vision, especially computer stereo vision has received extensive attention in recent years, and the demand for obtaining object depth information is increasing. For example, the positioning of intelligent security detection objects, three-dimensional positioning of drones, automatic driving obstacle judgment, robot navigation, 3D printing, etc. [0003] As we all know, in order to obtain depth information, a large amount of image data is processed and calculated, and the algorithm for image data processing is often complicated and computationally intensive. the complexity. However, just optimizing software algorithms cannot improve the efficiency of algorithm execution very well, and cannot keep up with the amount of data brought by the development of computer vision. Therefore, more and more researches focus on the des...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06T1/20
CPCG06T1/20
Inventor 刘劲松
Owner ALLWINNER TECH CO LTD