A method and device for controlling data transmission based on pcie bus

Abstract

The application provides a method for controlling data transmission based on the PCIe bus, wherein the method is applied to an FPGA with a direct memory access controller DMAC module, and the FPGA is connected to the CPU of a computer through the PCIe bus, the method Including: the DMAC module receives the direct memory access DMA command sent by the CPU; obtains the information of the external device specified in the DMA command, and sends the obtained information to the conversion module of FPGA, so that the conversion module obtains according to the information, determine the state of the external device, and the state of the target bus connecting the external device and the FPGA; after receiving the response sent by the conversion module according to the determined state, obtain the PCIe bus control right, and use the PCIe bus control right , according to the DMA instruction, control the FPGA and the memory of the computer to perform data transmission. Applying the solution of this application, a DMAC module is added to the FPGA to control the data transmission process of the PCIe bus to reduce the load on the CPU.

Description

technical field [0001] The present application relates to the field of computer technology, in particular to a method and device for controlling data transmission based on a PCIe bus. Background technique [0002] As a high-performance local bus, the PCIe (Peripheral Component Interconnect Express) bus is widely used in computer systems to connect CPUs and external devices. With the improvement and growth of computer system performance, functions and bandwidth, the CPU needs to be able to connect more external devices based on different protocols at the same time. Therefore, the PCIe protocol and other protocols can be realized through the rich external interfaces and internal resources of the FPGA. While converting, expand the number of PCIe ports. [0003] In the prior art, after the PCIe bus is connected to the CPU and the FPGA, when the CPU implements data transmission between the memory and the external device through the FPGA, the data transmission process between the...

AI Technical Summary

Problems solved by technology

[0003] In the prior art, after the PCIe bus is connected to the CPU and the FPGA, when the CPU implements data transmission between the memory and the external device through the FPGA, the data transmission process between the memory and the FPGA usually needs to be controlled by the CPU, and the CPU cannot perform other tasks before the transmission is completed. Work

Therefore, if a large amount of data needs to be transmitted between the CPU and the external device, this data transmission method will increase the load on the CPU and reduce the working efficiency of the computer system.

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