PCIe (Peripheral Component Interconnect Express) bus-based method and device of controlling data transmission

Abstract

The application provides a PCIe (Peripheral Component Interconnect Express) bus-based method of controlling data transmission. The method is characterized in that the method is applied to an FPGA witha direct-memory-access-controller (DMAC) module. The FPGA is connected with a CPU of a computer through a PCIe bus. The method includes: receiving a direct-memory-access (DMA) instruction, which is sent by the CPU, by the DMAC module; obtaining information of external equipment specified in the DMA instruction, sending the obtained information to a conversion module of the FPGA to enable the conversion module to determine status of the external equipment and status of a target bus, which connects the external equipment and the FPGA, according to the obtained information; and when response sent by the conversion module according to the determined status is received, obtaining PCIe bus control authority, and using the PCIe bus control authority to control the FPGA according to the DMA instruction for data transmission with memory of the computer. By applying the scheme of the application, the DMAC module is added in the FPGA to control a data transmission process of the PCIe bus, and loads of the CPU are alleviated.

Description

technical field [0001] The present application relates to the field of computer technology, in particular to a method and device for controlling data transmission based on a PCIe bus. Background technique [0002] As a high-performance local bus, the PCIe (Peripheral Component Interconnect Express) bus is widely used in computer systems to connect CPUs and external devices. With the improvement and growth of computer system performance, functions and bandwidth, the CPU needs to be able to connect more external devices based on different protocols at the same time. Therefore, the PCIe protocol and other protocols can be realized through the rich external interfaces and internal resources of the FPGA. While converting, expand the number of PCIe ports. [0003] In the prior art, after the PCIe bus is connected to the CPU and the FPGA, when the CPU implements data transmission between the memory and the external device through the FPGA, the data transmission process between the...

AI Technical Summary

Problems solved by technology

[0003] In the prior art, after the PCIe bus is connected to the CPU and the FPGA, when the CPU implements data transmission between the memory and the external device through the FPGA, the data transmission process between the memory and the FPGA usually needs to be controlled by the CPU, and the CPU cannot perform other tasks before the transmission is completed. Work

Therefore, if a large amount of data needs to be transmitted between the CPU and the external device, this data transmission method will increase the load on the CPU and reduce the working efficiency of the computer system.

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