A comparator offset voltage correction circuit and method with adjustable step size

Abstract

The invention relates to a comparator offset voltage correction circuit with adjustable step size, which includes a gate switch, a comparator, a step size selection control circuit, a charge pump switch control circuit and a charge pump, and the first input terminal of the gate switch receives the in-phase input signal V ip , the second input terminal of the strobe switch receives the inverting input signal V in , the common-mode input of the strobe switch receives the common-mode signal V cm ; The first correction control end of the gating switch is connected with the fourth output end of the step selection control circuit; the second correction control end of the gating switch is connected with the fifth output end of the step selection control circuit; One output terminal and the non-inverting input terminal V of the comparator in+ connection, the present invention realizes the adjustment of the correction step size, adopts a large correction step size in the early stage of the correction process, performs rough correction, and then adopts a small correction step size in the late stage of correction, and performs fine correction, so that the offset voltage of the comparator is corrected within the specified accuracy range.

Description

technical field [0001] The invention relates to the technical field of digital-analog hybrid integrated circuit design, in particular to a comparator offset voltage correction circuit and method with adjustable step size. Background technique [0002] As a key module in the digital-analog hybrid system, the analog-to-digital converter is widely used in many aspects of military and civilian fields. In recent years, with the continuous development of manufacturing technology and circuit design technology, the development of analog-to-digital converters has advanced by leaps and bounds. The comparator is a key module of the analog-to-digital converter, and its performance indicators such as accuracy, speed and power consumption have a crucial impact on the performance of the entire analog-to-digital converter system. High-speed and low-power comparators generally adopt the structure of a dynamic latch comparator, but this type of dynamic comparator has a large offset voltage. ...

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Problems solved by technology

It has the following disadvantages: 1. According to "A low-noise self-calibrating dynamic comparator for high-speed ADCs", the calibration step size needs to meet the system accuracy requirements. For a large range of misalignment, more calibration cycles are required

2. According to "A low-power dynamic comparator with digital calibration for reduced offset mismatch", add a variable capacitor array at the output load of the comparator, change the charge and discharge rate of the output node to reduce the offset voltage of the comparator, and the required correction The number of cycles is low, but the extra load capacitance added at the output node for this will affect the speed of the comparator, and the limited capacitor array makes the correctable comparator offset voltage range limited

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