A Parallel String Matching Algorithm Based on FPGA

A string matching and pattern string technology, applied in the field of information processing, to achieve the effect of good performance, flexibility and high matching rate

Active Publication Date: 2022-02-15
SUN YAT SEN UNIV
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  • Description
  • Claims
  • Application Information

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Problems solved by technology

Therefore, during the entire matching process, the i pointer does not backtrack

Method used

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  • A Parallel String Matching Algorithm Based on FPGA
  • A Parallel String Matching Algorithm Based on FPGA
  • A Parallel String Matching Algorithm Based on FPGA

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Embodiment 1

[0113] In order to explain the technical solution in detail, give how to realize the design of this solution in FPGA, and give an example, the pattern string P=abcdabd, the substring of the first j characters has been given in Table 2-2 , along with its prefix and suffix and the maximum common element length. Such as Figure 6 Shown is the parallel processing of this pattern string. The substrings corresponding to j=2 to j=6 are compared respectively, and each is regarded as a module, specifically:

[0114] j=2: compare a and b, if they are equal, output s1=1, otherwise s1=0;

[0115] j=3: compare a and c, ab and bc, if they are equal, output s2=1, s3=1, otherwise s2=0, s3=0;

[0116] j=4: compare a and d, ab and cd, abc and bcd, if they are equal, output s4=1, s5=1, s6=1, otherwise s4=0, s5=0, s6=0;

[0117] j=5: Compare a and a, ab and da, abc and cda, abcd and cdba, if they are equal, output s7=1, s8=1, s9=1, s10=1, otherwise s7=0, s8=0 , s9=0, s10=0;

[0118] j=6: co...

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Abstract

The present invention relates to a parallel character string matching algorithm based on FPGA, realizes finding the substring of the first j characters of a pattern character string in one clock cycle, and the maximum common element value of its prefix and suffix through FPGA parallel processing, through the prefix The maximum common element value of and suffix can be directly obtained and output as a NEXT array, and the parallel matching of multiple pattern strings can be realized by using the NEXT array.

Description

technical field [0001] The present invention relates to the field of information processing, and more specifically, relates to an FPGA-based parallel character string matching algorithm. Background technique [0002] With the continuous development of computer hardware, the parallel processing of data by CPU and coprocessor in servers and terminals has been widely used, especially the acceleration of FPGA in data-intensive computing. FPGA has significant advantages such as reconfigurability and high degree of parallelization, and has become a commonly used acceleration device. In recent years, more and more FPGA parallel processing architectures are deployed based on data centers, and complex algorithms are accelerated using FPGA hardware resources. A new way to optimize performance. For the string matching algorithm in the process of information processing, at present, there are more classic KMP algorithm, BM algorithm and a QS algorithm based on the improvement of BM algo...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F16/9032
Inventor 黄以华殷海元
Owner SUN YAT SEN UNIV
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