Phase change memory-based mapping management method and solid-state hard disk

Abstract

The invention discloses a phase change memory-based mapping management method and a solid-state hard disk, which is characterized in that two-level mapping table management is adopted and specificallycomprises a first level table and a second level table; the second level table is stored in the phase change memory PCM; the second level table records the relationship between the logical address and the physical address of all the user data pages; the second level table is divided into a plurality of second level table sub-units according to the granularity G; and the second level table sub-unit is used as a basic unit for cache of a hard disk controller to carry out data replacement; and by introducing the phase change memory for storing a mapping table, the read-write time of the phase change memory is much lower than that of NAND. According to the phase change memory-based mapping management method and the solid-state hard disk in the invention, the phase change memory is introducedin the NODRAM solid-state hard disk to replace the NAND for saving the complete mapping table; the time of the mapping table cache in the on-chip SRAM replacing the mapping table information is reduced, thereby achieving the effect of reducing the read-write instruction completion time and improving the read-write performance.

Description

technical field [0001] The invention relates to the field of storage technology, in particular to a phase-change memory-based mapping management method and a solid-state hard disk. Background technique [0002] In the existing solid-state hard disk system without DRAM, because of the space limitation of the on-chip SRAM, it is not enough to store the entire mapping table (the mapping table refers to the table that records the mapping relationship between the logical address of the data page and the NAND physical address), and the complete mapping table Stored in NAND, a cache cache is maintained in the on-chip SRAM, and part of the mapping table is cached in the cache, that is, the recently accessed data page logical address to physical address mapping relationship. In the random read / write scenario of the host HOST, the system needs to frequently exchange mapping table information with the NAND, and the HOST read / write takes a long time to complete and the performance is lo...

AI Technical Summary

Problems solved by technology

In the scenario where the host HOST reads and writes randomly, the system needs to frequently exchange mapping table information with NAND, and the HOST reads and writes take a long time to complete and the performance is low

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