38results about How to "Shorter read and write times" patented technology

The present invention discloses a semiconductor memory device comprising a source, a drain, a floating gate, a control gate, a recess channel and a gated p-n diode. The said p-n diode connects said floating gate and said drain. The said floating gate is for charge storage purpose, it can be electrically charged or discharged by current flowing through the gated p-n diode. An array of memory cells formed by the disclosed semiconductor memory device is proposed. Furthermore, an operating method and a method for producing the disclosed semiconductor memory device and array are described.

A semiconductor memory device able to strengthen an error correction capability, able to shorten a write time and / or a read time, able to make a redundant memory unnecessary or smaller, and consequently able to achieve a reduction of size and a reduction of cost, provided with a data input portion for receiving 1 page's worth of data, dividing it to a plurality of code words, generating and adding check code (parity data) for each code word, successively forming main code words and transferring the same to a bank (A) or a bank (B), and a data output portion for receiving 1 page's worth of data including main code words transferred from the data latch circuit, correcting the error data when there is within a predetermined number of error data for each main code word, adding the error information for read each read code word except check code (parity data), and transferring the same to a host side, and a signal processing system using the same.

In a memory cell, a transistor with extremely high off-resistance is used as a write transistor; a drain and a source of the write transistor are connected to a write bit line and an input of an inverter, respectively; and a drain and a source of a read transistor are connected to a read bit line and an output of the inverter, respectively. Capacitors may be intentionally disposed to the source of the write transistor. Alternatively, parasitic capacitance may be used. Since the data retention is performed using charge stored on these capacitors, a potential difference between power sources for the inverter can be 0. This eliminates leakage current between the positive and negative electrodes of the inverter, thereby reducing power consumption.

Provided are a transistor of a semiconductor device and a method for manufacturing the same. A gate induced drain leakage (GIDL) current is reduced by decreasing a work function at an upper portion of a gate electrode, and a threshold voltage of the transistor is maintained by maintaining a work function at a lower portion of the gate electrode at a high level, thereby reducing a leakage current of the transistor and reducing a read time and a write time of the semiconductor device. The transistor of the semiconductor device includes: a recess with a predetermined depth in a semiconductor substrate; a first gate electrode disposed within the recess; and a second gate electrode disposed on the first gate electrode into which ions of one or more of nitrogen (N), oxygen (O), arsenic (As), aluminum (Al), and hydrogen (H) are doped.

The present invention provides a data reading and writing method, a reading and writing device and a DRAM. The reading and writing method includes: entering a page reading and writing mode, and the page reading and writing mode is configured through a reserved bit in a mode register of the DRAM . A page read / write command is received, including a page read / write enable command, and the page read / write enable command is configured through a reserved bit of the read / write command of the DRAM. Perform page read and write operations according to the page read and write commands. The reading and writing method of the present invention enables each reading and writing command to read and write a large amount of data, reduces the number of times of sending the reading and writing commands, improves the reading and writing speed, and reduces power consumption.

The present invention discloses a crash analysis method and system for binary programs, including steps: S1, information collection and processing, in this step, the instrumentation module performs code instrumentation on multiple key positions and basic blocks, and then runs the program , record information; the taint module takes the program input as taint, tracks the spread of taint during program execution, and at the same time, performs symbolic operation on each executed instruction, and finally performs reverse slice from the crash point according to the symbolic content , record information; S2, analyze based on the data processed in step S1, and obtain the program execution trajectory diagram, stain propagation trajectory diagram and crash causes, etc.; the present invention can analyze the program without source code, and collect the program running Crash information, crash backtracking, locating the crash point, determining the cause of the crash, etc., greatly reduces the cost of manual analysis, and can assist vulnerability analysts to quickly determine the mechanism of the program crash.

The invention provides a data reading and writing method, a reading and writing device and a dynamic random access memory, which enters a page reading and writing mode according to a mode selection command, and the page reading and writing mode command is configured through the mode register of the dynamic random access memory; receiving page reading The write command includes a page read-write enable command and an interleave read command, the page read-write enable command is configured through the first reserved bit of the read-write command of the DRAM, and the interleave read command is configured through the The second reserved bit of the read and write command of the dynamic random access memory is configured, and the interleave read command is used to control the interleave read and write data in a plurality of memory block groups; according to the page read and write command, perform the interleave Page read and write operations.

The invention discloses a rapid-reading-writing electric-power-system PQ-decomposition-method flow data storage method based on the sparse technology.The method includes the step that nonzero elements at the upper triangles and the lower triangles of arrays of Y(n, 2n), B'(n-1, n-1) and B''(m, m) in a traditional method are stored into an A(n, d) array formed by three virtual arrays of Y(n, d<1>), B'(n-1, d<2>) and B''(m, d<3>).The number of storage units is greatly decreased, the reading-writing speed of a data file and the calculating speed of I<pi> or I<qi> or P or Q during PQ-decomposition-method flow calculation are increased, the number of the storage units is also greatly decreased, and efficiency is greatly improved.Compared with the traditional method, the method has the advantages that as for an IEEE-118 node system, the largest number of the storage units is only 14.69% of that of the traditional method, the practical number of the storage units is only 6.66% of that of the traditional method, the data file writing time and the data file reading time are 14.32% and 7.29% of the data file writing time and the data file reading time of the traditional method respectively, and the larger the number of nodes is, the more obvious the advantages of the method are.