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Data reading and writing method and device, dynamic random access memory

A dynamic random, data read and write technology, applied in the field of memory, can solve the problems of small memory read and write length, limited read and write speed, etc., to reduce data read and write time, improve read and write speed, and save costs.

Active Publication Date: 2022-06-28
CHANGXIN MEMORY TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] The purpose of the present invention is to provide a method for reading and writing data, a device for reading and writing and a dynamic random access memory, so as to solve the problems in the related art that the read and write length of the memory is small and the read and write rate is limited

Method used

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  • Data reading and writing method and device, dynamic random access memory
  • Data reading and writing method and device, dynamic random access memory
  • Data reading and writing method and device, dynamic random access memory

Examples

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Embodiment Construction

[0040] Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments, however, can be embodied in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus their detailed descriptions will be omitted.

[0041] like figure 1 As shown, most of the current SoCs use AXI interface as the interface for direct memory access (DMA, Direct Memory Access) to access dynamic random access memory (DRAM, Dynamic Random Access Memory), for example, GPU / VEDIE / DISPLAY accesses DRAM through AXI interface, The bit width (axi_size) of the data in the corresponding AXI command is usually 256 bits, and the length of the data is usually 8 or 16,...

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PUM

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Abstract

The invention provides a data reading and writing method, a reading and writing device and a dynamic random access memory, which enters a page reading and writing mode according to a mode selection command, and the page reading and writing mode command is configured through the mode register of the dynamic random access memory; receiving page reading The write command includes a page read-write enable command and an interleave read command, the page read-write enable command is configured through the first reserved bit of the read-write command of the DRAM, and the interleave read command is configured through the The second reserved bit of the read and write command of the dynamic random access memory is configured, and the interleave read command is used to control the interleave read and write data in a plurality of memory block groups; according to the page read and write command, perform the interleave Page read and write operations.

Description

technical field [0001] The present invention relates to the technical field of memory, in particular, to a data reading and writing method, a reading and writing device and a dynamic random access memory. Background technique [0002] With the rapid development of memory, people expect the memory to provide faster and faster read and write rates and lower power consumption. [0003] Generally, the data required by the command to access the memory is often large, and the read and write length supported by the current memory is small. Therefore, multiple read and write commands need to be sent to process one access data, and the read and write rate is limited. In addition, when each read and write command is sent, various processing circuits inside the memory are flipped, and the power consumption is high, resulting in high power consumption of the entire memory. [0004] It should be noted that the information disclosed in the above Background section is only for enhancing u...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F12/06
CPCG06F12/0646
Inventor 邓升成
Owner CHANGXIN MEMORY TECH INC
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