Unlock instant, AI-driven research and patent intelligence for your innovation.

Fabrication method of mos transistor with hkmg

A technology of MOS transistors and manufacturing methods, which is applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve problems such as polysilicon gate height load, and achieve the effect of preventing polysilicon residues and preventing defects

Active Publication Date: 2020-11-24
SHANGHAI HUALI INTEGRATED CIRCUIT CORP
View PDF7 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] In the existing method, the dummy polysilicon gates in each region are removed at the same time. Before removing the dummy polysilicon gates, the front layer will have a polysilicon gate height (gate high) between the NFET and the PFET due to the different processes of the NFET (NMOS) and the PFET (PMOS). load

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Fabrication method of mos transistor with hkmg
  • Fabrication method of mos transistor with hkmg
  • Fabrication method of mos transistor with hkmg

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0035] Existing methods:

[0036] Such as Figure 1A to Figure 1D Shown is a schematic diagram of the structure of the device in each step of the existing MOS transistor manufacturing method with HKMG. The existing MOS transistor manufacturing method with HKMG includes the following steps:

[0037] Step one, such as Figure 1A As shown, the MOS transistor includes NMOS and PMOS, a dummy gate structure is formed on the surface of the semiconductor substrate 101, a source and drain region 109 of NMOS, a source and drain region 108 of PMOS, sidewalls 107, a contact hole etch stop layer 110 and an interlayer film 111, the dummy gate structure is formed by stacking a gate dielectric layer and a dummy polysilicon gate 106; the interlayer film 111 is planarized by a chemical mechanical polishing (CMP) process, and the dummy polysilicon The surface of the grid 106 is exposed.

[0038] Usually, the semiconductor substrate 101 is a silicon substrate.

[0039] The material of the sid...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

PropertyMeasurementUnit
lengthaaaaaaaaaa
lengthaaaaaaaaaa
Login to View More

Abstract

The invention discloses a method for manufacturing an MOS transistor with an HKMG. The method comprises: step one, forming a pseudo gate structure until forming of an interlayer film and carrying outplanarization; step two, forming a first photoresist pattern and opening a PMOS region; step three, removing a pseudo polysilicon gate in the PMOS region; step four, forming a first work function layer corresponding to the PMOS; step five, forming a second photoresist pattern and opening an NMOS region; step six, removing the first work function layer and the pseudo polysilicon gate in the NMOS region; step seven, forming a second work function layer corresponding to the NMOS; step eight, forming a metal material layer of a metal gate; and step nine, carrying out planarization on the metal material layer. Therefore, the pseudo polysilicon gate can be removed well; and defects caused by different etching loads of the pseudo polysilicon gates with different heights are overcome.

Description

technical field [0001] The invention relates to a method for manufacturing a semiconductor integrated circuit, in particular to a method for manufacturing a MOS transistor with HKMG. Background technique [0002] HKMG has a gate dielectric layer with a high dielectric constant (HK) and a metal gate (MG), so it is usually abbreviated as HKMG in the art. In the existing method, the process node of HKMG reaches below 28nm. [0003] In the existing method, the dummy polysilicon gates in each region are removed at the same time. Before removing the dummy polysilicon gates, the front layer will have a polysilicon gate height (gate high) between the NFET and the PFET due to the different processes of the NFET (NMOS) and the PFET (PMOS). loading. In the case that the CMP process window of the interlayer film is not enough, SiN or even Oxide, that is, the oxide layer may remain on some patterns, thereby causing some defects. Contents of the invention [0004] The technical probl...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/8238
CPCH01L21/8238
Inventor 郭震张志诚
Owner SHANGHAI HUALI INTEGRATED CIRCUIT CORP