FPGA implementation method for Cholesky decomposition of positive definite matrix

An implementation method, a positive definite matrix technology, applied in complex mathematical operations, etc., to achieve high data throughput, reduce computational complexity and the effect of gate circuit area

Inactive Publication Date: 2018-11-02
NANJING UNIV
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Problems solved by technology

[0003] In order to solve the computational complexity and resource consumption problems of the Cholesky decomposition of positive definite matrices, the present invention uses the rotation characteristics of the CORDIC algorithm to calculate the

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  • FPGA implementation method for Cholesky decomposition of positive definite matrix
  • FPGA implementation method for Cholesky decomposition of positive definite matrix
  • FPGA implementation method for Cholesky decomposition of positive definite matrix

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Embodiment Construction

[0036] The solution of the present invention will be described in detail below in conjunction with the accompanying drawings.

[0037] Such as figure 1 As shown, the FPGA implementation method of Cholesky decomposition of a positive definite matrix in this embodiment is mainly composed of a top-level control module, a data preprocessing module and a matrix calculation module. The data is first input to the data preprocessing module, and the state transition is controlled by the top-level control module. After the data preprocessing is completed, the top-level control module controls the flow of data to the matrix calculation module, and controls the matrix calculation module to process the data. After the matrix Cholesky decomposition is completed , the top-level control block allows output of result data.

[0038] Such as figure 2 As shown, the data input from the outside world is temporarily stored in the input FIFO, and then sent to the data preprocessing module for proc...

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Abstract

The present invention discloses an FPGA implementation method for Cholesky decomposition of a positive definite matrix. The method is mainly provided with: a top layer control module, for communication and control between modules; a data preprocessing module, for decomposing a positive definite matrix into two matrices for calculation operations in a matrix calculation module; and the matrix calculation module, for calculating two matrices obtained by the data preprocessing module to obtain a final Cholesky decomposition calculation result. Beneficial effects of the method disclosed by the present invention are that: by using the traditional hardware to directly implement Cholesky decomposition of the positive definite matrix, the algorithm is complex, the occupied area is large, and the resource consumption is more, and by using the rotation characteristic of the CORDIC algorithm to implement the Cholesky decomposition of the positive definite matrix, the implementation is simple, only the bit operation is needed, the resource consumption is less, and the computational complexity and the area of the gate circuit are effectively reduced.

Description

technical field [0001] The invention belongs to the field of digital signal processing, in particular to an FPGA realization method of Cholesky decomposition of a positive definite matrix. Background technique [0002] The Cholesky decomposition of a positive definite matrix is ​​a very important form of matrix triangulation decomposition, which is widely used in scientific computing, communication, and spectrum analysis. However, the Cholesky decomposition of a positive definite matrix with a scale of n×n requires a large number of multiplication and square root operations, and the computational complexity is O(n 3 / 6), therefore, under the condition that n is very large, the Cholesky decomposition calculation of the matrix has a huge amount of calculation, and the hardware implementation consumes a lot of resources. Contents of the invention [0003] In order to solve the computational complexity and resource consumption problems of the Cholesky decomposition of positiv...

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Application Information

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IPC IPC(8): G06F17/16
CPCG06F17/16
Inventor 潘红兵孙华庆罗元勇何书专李丽李伟
Owner NANJING UNIV
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