Method for improving timing margin of NandFlash bus

Abstract

The present invention discloses a method for improving the timing margin of a NandFlash bus. The method comprises the following steps: calculating a load capacitance value according to a storage capacity; determining a target capacitance value according to a signal rise time requirement; and serially connecting a series capacitor to the DQ and DQS signals, and determining a capacitance value of aseries capacitor according to the load capacitance value and the target capacitance value. According to the method for improving the timing margin of a NandFlash bus disclosed by the present invention, by using the principle that after two capacitors are connected in series, the equivalent capacitance is smaller than the capacitance of any one of the series capacitors, and by serially connecting the series capacitors in the IO signal link, the timing margin of the bus is improved, the contradiction between the large capacity and the high speed is solved, and consideration of both of the largecapacity and the high speed can be achieved.

Description

technical field [0001] The invention relates to the technical field of storage, in particular to a method for improving the timing margin of a NandFlash bus. Background technique [0002] With the advent of the big data era, the demand for "increasing the storage capacity per unit volume of a product" and "reducing the delay of the entire system" is becoming stronger and stronger. "Large capacity" means that the number of dies mounted on a single channel on the NandFlash bus must gradually increase, and the load capacitance is getting larger and larger; "Low latency" means that the operating speed requirements of the NandFlash bus will also be higher and higher. However, the larger the load capacitance of the system, the more serious the edge degradation of the running signal, the smaller the timing margin window to meet the system requirements, and the lower the allowable running speed—that is, "large capacity" and "high speed" in NandFlash On the bus is a paradoxical pres...

AI Technical Summary

Problems solved by technology

However, the larger the load capacitance of the system, the more serious the edge degradation of the running signal, the smaller the timing margin window to meet the system requirements, and the lower the allowable running speed—that is, "large capacity" and "high speed" in NandFlash On the bus is a paradox

The operating speed of the NandFlash bus has become the bottleneck restricting the improvement of the entire storage performance

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