LinkPort communication system and method based on FPGA

Abstract

The invention discloses a LinkPort communication system and method based on an FPGA, and the method comprises the steps: a receiving step: receiving a bus input clock by a receiving module, taking the bus input clock as a trigger clock of an IDDR circuit, capturing bus data, converting the bus data into single-rate data, capturing data outputted by the IDDR circuit by using a register set, storing data captured by a register group into a data buffer area, and when data needs to be sent, outputting the data from the data buffer area by a receiving module in a data frame form, and entering a sending step: generating 0-degree and 270-degree clocks with the same frequency as a bus clock by a phase-locked loop circuit; enabling the 0-degree clock driving data ODDR circuit to receive the data and generate the bus output data, and enabling the 270-degree clock driving clock ODDR circuit to generate a bus output clock; after sending of one frame of data is completed, carrying out the sending of the next frame of data. Therefore, the maximum 125MHz bus communication rate supported by the LinkPort protocol is realized, the time sequence margin is increased, and the method can be applied to a relatively low-end FPGA.

Description

technical field [0001] The invention relates to the field of FPGA technology, in particular to an FPGA-based LinkPort communication system and method. Background technique [0002] Such as figure 1 As shown, the LinkPort interface is in half-duplex mode, and it can also be used as a simplex mode. The essence of the link layer of the protocol is the source synchronous interface (Source Synchronous Interface) of DDR (Double Data Rate, double rate) transmission. With 128bit data frame as the transmission granularity, each frame of data requires 8 bus clocks. Each LinkPort interface has both an input clock and an output clock signal. The clock signal is not only used to synchronize data, but also used to complete the communication control function. figure 2 Shown is the LinkPort link layer communication protocol (only a partial illustration). In the figure, the LxCLKOUT output clock is a discontinuous clock, which is used for bus request (TOKEN REQUEST) and for synchronizing...

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Problems solved by technology

However, the performance of the FPGA used in this article is high, and it is stated that manual optimization is required in the layout and routing stage. At the same time, the physical layer of the TS201 LinkPort interface itself uses high-speed LVDS signals, and finally achieves a bus frequency of 300MHz. However, the solution is the key to how to achieve high performance. Design is not exhaustive and cannot be applied to low-end FPGAs

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