Reading dqs signal gate gating training method, device and data transmission system

Abstract

The invention provides a DQS signal reading gate selection training method, device and a data transmission system. The method comprises the following steps: generating a gate selection enabling signal, the width of which is clock period width of BL / 2-1 DQS reading signal first and then controlling the gate selection enabling signal to move from left to right till the falling edge of the gate selection gate enabling signal just exceeds the last but one rising edge of the DQS reading signal to obtain a moved gate selection enabling signal; delaying the moved gate selection enabling signal to obtain a delayed gate selection enabling signal; and then obtaining a final gate selection window port of the DQS reading signal by taking the raising edge of delayed gate selection enabling signal as astarting position of the gate selection window port and taking the position of the last falling edge of the DQS reading signal as a finish position of the gate selection window. The time sequence overmeasure of a DQS signal gate selection training result can be improved greatly, and the working stability of the system is enhanced.

Description

technical field [0001] The invention relates to the field of data access technology, in particular to a method, device and data transmission system for reading DQS signal gate gating training. Background technique [0002] DDR (Double Data Rate, double rate) system is the habitual abbreviation of DDR SDRAM (Synchronous Dynamic Random Access Memory, double data transmission rate synchronous dynamic random access memory) system, its advantages are large storage capacity, low cost, mature interface, Moreover, during parallel burst access, a higher access rate can be achieved. [0003] Please refer to figure 1 As shown, in general, a DDR system is mainly composed of a controller DDRC, a physical layer DDR PHY, a memory particle DRAM, and a bus between them. The signals transmitted on the bus mainly include clock signal CLK, command signal CMD, address signal ADDR, data signal DQ and read strobe signal DQS (also called data sampling signal, data strobe signal or read DQS signal...

AI Technical Summary

Problems solved by technology

When the read DQS signal sent by DRAM changes from high impedance (High Z) to logic low level (0, logic low) or from low level (0) to high impedance (High Z), due to parasitic inductance and capacitance, etc. Ideality factor, the signal will oscillate (glitch, such as figure 2 Marked by the dotted circles at the beginning and end of the real DQS waveform in ), these oscillations will be converted to digital logic "1" by the DDR PHY front-end receiver, causing the read DQS signal output by the DDR PHY front-end receiver to be in the preamble (preamble) and Glitch (glitch, such as figure 2 The dotted circles at the beginning and end of the read DQS signal output by the DDR PHY front-end receiver are marked), and the read DQS signal with glitches will cause wrong data reception (that is, the DDR PHY read data error)

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