A Design Method for Mixed Height Cell Layout Based on Minimum Implanted Area Constraint

Abstract

The present invention provides a mixed-height cell layout design method based on minimum implantation area constraints, which includes the following steps: step S1: fast global layout; step S2: applying graph-based clustering and reshaping to cells with MIA conflicts in the horizontal direction ; Step S3: Legalization based on MIA constraints; Step S4: Assign and optimize the location of the unit. By adding weighted virtual nets, HVT / LVT cells with the same voltage are placed closer to each other. The Vdd / Vss constraint is characterized by the cost function, and the variation of the line length can be minimized globally; the graph-based clustering method and the matching-based method are used to compress the area area and reduce the use of filler; The constraints based on the vertical MIA are transformed into QP problems and solved using the MMSIM solver; in order to further optimize the layout results, the cell allocation and cell location optimization are also performed at the end.

Description

technical field [0001] The invention belongs to the technical field of VLSI physical design automation, and provides a mixed-height cell layout design method based on minimum implantation area constraints. Background technique [0002] In traditional circuit design, standard cells usually have the same height for ease of design and optimization. However, in modern circuit designs, using standard cells with different row heights can achieve better design trade-offs among latency, power, and routability. Specifically, taller cells can give greater driving force and better routability, but also require larger area and power costs. The circuit design of such mixed-height cells is more challenging due to the heterogeneous cell structure (resulting in more global cell disturbances and an increase in the solution space). Also, in this layout design, additional consideration needs to be given to aligning multiple row height cells to the correct power (Vdd) and ground (Vss) rails. ...

AI Technical Summary

Problems solved by technology

However, with the reduction of cell feature size, and due to the limitation of lithography technology, the layout of multi-threshold voltage cells may violate the MIA constraints.

Images