Loading circuit and loading method for improving serial passive loading rate of FPGA

Abstract

The invention discloses a loading circuit and a loading method for improving the serial passive loading rate of an FPGA. The method of utilizing multiplexing of a serial interface clock pin and an FPGA serial passive loading clock pin and generating, by a processor, a configuration clock signal required for loading the FPGA is utilized to achieve a function of causing an FPGA chip to directly reada configuration file from a FLASH chip to complete loading. According to the method, the problem of slow passive loading of the low-rate serial interface FPGA is solved mainly. Compared with conventional FPGA passive loading, the loading circuit and the loading method have the advantages of quick loading speed and simple design. The loading circuit and the loading method can be applied to any hardware platform that uses a serial interface for passive loading of the FPGA.

Description

technical field [0001] The invention relates to a loading circuit and a loading method for improving the FPGA serial passive loading rate, which is particularly suitable for serial interface loading and belongs to the field of embedded signal processing. Background technique [0002] There are many ways to load FPGA, and the commonly used ways are active loading and passive loading. [0003] For FPGA active loading, the current solutions all require a dedicated configuration chip and must use a dedicated JTAG interface. However, the configuration chip and the JTAG interface occupy a large area, which cannot meet the requirements of miniaturized design; meanwhile, this method cannot realize flexible online upgrade. [0004] FPGA passive loading is divided into serial passive loading and parallel passive loading according to the interface mode. Usually parallel passive loading is faster, but requires more peripheral interfaces. Serial passive loading uses few peripheral int...

AI Technical Summary

Problems solved by technology

However, serial passive loading needs to simulate the timing of passive loading. For ordinary low-speed processors, each operation step requires several instructions, which is time-consuming.

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