Logic level conversion circuit and integrated circuit

Abstract

The embodiment of the invention provides a logic level conversion circuit and an integrated circuit, applied to a cascaded chip, the cascaded chip comprises N levels of chips connected in series, theN is an integer greater than 1, the logic level conversion circuit is connected between the (M-1)th level chip in the cascaded chip and the Mth level chip in the cascaded chip, and the M is an integergreater than 1 and less than or equal to N; the logic level conversion circuit is used for converting the voltage of a level signal into a target voltage when the (M-1)th level chip transmits the level signal to the Mth level chip, and sending the level signal in which the voltage is the target voltage to the Mth level chip; and the target voltage is matched with a working voltage of the Mth level chip. By application of the logic level conversion circuit provided by the embodiment of the invention, the following problems are avoided: an IO port is damaged due to a negative pressure, and thebit error rate is increased due to lower than the normal working voltage, resulting in communication failure.

Description

technical field [0001] The invention relates to the technical field of electronic circuits, in particular to a logic level conversion circuit and an integrated circuit. Background technique [0002] With the development of electronic technology, there are more and more various electronic devices to meet people's different needs, such as electronic devices that need to use many chips for specific data processing. [0003] At present, for electronic equipment with many chips, such as special-purpose computing equipment, the chips are cascaded applications. The so-called cascaded application refers to connecting multiple circuit structures with the same or similar functions in a regular connection manner. Specifically, Chip cascading means that the negative pole of the power supply of the upper chip is connected to the positive pole of the power supply of the lower chip. At present, some schemes connect the two chips directly, and some schemes add resistors between the two chip...

AI Technical Summary

Problems solved by technology

[0005] When the lower-level chip U 1 To the upper chip U 2 When the transmitted level signal is high level, the upper chip U 2 The high-level voltage of the received level signal is VIO-Vcore. When the high-level voltage of VIO-Vcore is lower than the normal high-level VIO voltage, the bit error rate will be greatly increased, resulting in communication failure.

[0006] Assuming Vcore=0.4V, VIO=1.8V, the voltage difference of the same logic level between different level chips is 0.4V, that is, when the lower level chip U 1 To the upper chip U 2 The low level of the transmitted level signal is 0V, and the upper chip U 2 The low-level voltage of the received level signal is -0.4V, which will cause damage to the IO port; when the lower-level chip U 1 To the upper chip U 2 When the high level of the transmitted level signal is 1.8V, the upper chip U 2 The high level of the received level signal is 1.4V, if it is lower than 1.8V, the bit error rate will be greatly increased, resulting in communication failure

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