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Enlarged sacrificial gate cover for forming self-aligned contacts

A covering and gate electrode technology, applied in the field of sacrificial gate covering and self-aligned contacts, can solve problems such as damage to field effect transistors, short circuits, etc.

Active Publication Date: 2021-08-31
GLOBALFOUNDRIES U S INC MALTA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Otherwise, a short circuit may occur which may damage the FET

Method used

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  • Enlarged sacrificial gate cover for forming self-aligned contacts
  • Enlarged sacrificial gate cover for forming self-aligned contacts
  • Enlarged sacrificial gate cover for forming self-aligned contacts

Examples

Experimental program
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Embodiment Construction

[0011] Please refer to figure 1 And according to an embodiment of the present invention, a substrate 10 is provided, which can be a bulk substrate or a device layer of a semiconductor-on-insulator (SOI) substrate. Gate structure 12 is located on the top surface of substrate 10 . Segments of interlayer dielectric layer 14 are located in spaces between gate structures 12 . Each gate structure 12 includes a gate dielectric 16 and a gate electrode 18 . Vertical sidewalls of the gate structure 12 are covered by side spacers 20 .

[0012] The interlayer dielectric layer 14 can be made of a dielectric material such as silicon dioxide (SiO 2 ))composition. The gate dielectric 16 may be composed of a dielectric material deposited by atomic layer deposition (atomic layer deposition; ALD), such as a high-k dielectric material such as hafnium oxide (HfO 2 ), which has higher than SiO 2 The dielectric constant of the dielectric constant. The gate electrode 18 may include a conducto...

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PUM

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Abstract

The present invention relates to enlarged sacrificial gate caps for forming self-aligned contacts, which discloses methods of forming sacrificial gate caps and self-aligned contacts for device structures. A gate electrode is disposed between the first side spacer and the second side spacer. The top surface of the gate electrode is recessed to create a space above the top surface of the recessed gate electrode, which partially exposes the first and second side spacers. Respective portions of the first and second side spacers disposed on the top surface of the recessed gate electrode are removed to increase the width of the space. A sacrificial covering is formed in this widened space.

Description

technical field [0001] The present invention relates to semiconductor device fabrication and integrated circuits, and more particularly to methods of forming sacrificial gate caps and self-aligned contacts for device structures such as field effect transistors. Background technique [0002] The device structure of a field effect transistor generally includes a body region, a source and a drain defined in the body region, and a gate structure configured to apply a control voltage that switches a device formed in the body region. carrier flow in the channel. When a control voltage greater than a specified threshold voltage is applied, carrier flow occurs in the channel between the source and drain, resulting in a device output current. [0003] The contacts may provide vertical electrical connections to features of the semiconductor device, such as gate structures and source / drain regions of field effect transistors. During etching, self-aligned contacts (self-aligned contac...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/336H01L21/28
CPCH01L21/28017H01L21/28247H01L29/66621H01L29/66636H01L21/76834H01L21/76897H01L21/28132
Inventor A·K·杰哈王海艇张志强M·卢特考斯基
Owner GLOBALFOUNDRIES U S INC MALTA