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An optimized scheduling method for dram memory encapsulation process

A technology for optimizing scheduling and optimizing algorithms, which is applied in the direction of program control, electrical program control, control/regulation system, etc., can solve problems such as low economic benefit, waste of electric energy, and increased cost, so as to increase economic benefit, reduce power consumption, Address inefficiencies

Active Publication Date: 2021-07-16
KUNMING UNIV OF SCI & TECH
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Problems solved by technology

[0006] The purpose of the present invention is to propose a kind of optimal scheduling method based on dynamic programming dual-objective optimization algorithm aiming at the scheduling problem of the DRAM memory product packaging process, to solve the time waste and cost increase caused by improper process arrangement in the DRAM memory product packaging process. Low economic benefit and waste of electric energy

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  • An optimized scheduling method for dram memory encapsulation process
  • An optimized scheduling method for dram memory encapsulation process
  • An optimized scheduling method for dram memory encapsulation process

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Embodiment 1

[0026] Embodiment 1: as Figure 1-4 As shown, an optimal scheduling method of a DRAM memory packaging process, firstly establishes a scheduling model of the DRAM memory product packaging process based on a sorting model and an optimization target; then designs an optimal scheduling method based on a dynamic programming dual-objective optimization algorithm to optimize the target; Finally, the proposed algorithm is verified under different problem scales;

[0027] The basis for establishing the scheduling model is the quantity of DRAM memory products to be packaged, the processing time, and the power consumption during the processing process. The first optimization goal is the total flow time (Total Flow Time, TFT) The second optimization objective is the total electric energy consumption (Total Electric Energy Consumption, TEEC) of the machining process: f 2 =TEEC:

[0028]

[0029] f j = c j-1 +p j ,j∈{1,...,n|n∈N*}

[0030] TEEC=C p +C t +C i

[0031]

[003...

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Abstract

The invention relates to an optimization scheduling method of a DRAM memory packaging process, belonging to the technical field of intelligent optimization scheduling of semiconductor processing and production processes. The present invention firstly establishes the scheduling model and optimization target of the packaging and processing process of DRAM memory products based on the sorting model; then designs an optimal scheduling method based on a dynamic programming dual-objective optimization algorithm to optimize the target; and finally verifies the proposed algorithm under different problem scales . The present invention can obtain an approximate optimal solution to the scheduling problem of the packaging and processing process of DRAM memory products in a short time, so as to achieve the effects of improving the production efficiency of the factory, increasing economic benefits, and reducing power consumption, and can effectively solve the problem of packaging and processing of DRAM memory products. Inefficiency and waste of resources and energy due to improper arrangement of processes.

Description

technical field [0001] The invention relates to an optimization scheduling method of a DRAM memory packaging process, belonging to the technical field of intelligent optimization scheduling of semiconductor processing and production processes. Background technique [0002] With the rapid development of the artificial intelligence industry, various artificial intelligence products gradually meet the various needs of people's life and work, greatly improving the labor efficiency of all walks of life, reducing production costs, and bringing huge economic and social benefits. social benefits. As an important component almost as important as the CPU, DRAM memory products are an indispensable part of various intelligent electronic products. Since the reform and opening up, my country, as the world's factory, has become the world's largest manufacturer of electronic components. The replacement speed of electronic components is extremely fast, so the requirements for production ef...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G05B19/418
CPCG05B19/41865G05B2219/32252Y02P90/02
Inventor 钱斌张洪琳胡蓉
Owner KUNMING UNIV OF SCI & TECH
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