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A dual-chip loading method based on mcu and fpga

A dual-chip, chip technology, applied in the field of electronics, achieves the effect of reducing memory size dependence, reducing complexity, and saving startup loading time

Active Publication Date: 2021-03-30
BEIJING DAHENG IMAGE VISION +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] And the present invention has adopted a kind of special connection structure and loading method, has solved this problem

Method used

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  • A dual-chip loading method based on mcu and fpga
  • A dual-chip loading method based on mcu and fpga
  • A dual-chip loading method based on mcu and fpga

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0032] figure 1 A schematic diagram of a connection manner of a two-chip structure is shown. Such as figure 1 Shown, in this embodiment, MCU is connected with FLASH through four pins of SPI: CS, MOSI, MISO, CLK, can independently read and write FLASH; CCLK and DIN of FPGA are connected with CLK and MISO of MCU end respectively, like this Connect the FPGA to receive the clock of the MCU and the data output by the FLASH.

[0033] In addition, in this embodiment, the FPGA is configured as a slave serial configuration mode. In this mode, the program can be passively serially loaded, and the configuration file required for loading is in .bin format; the MCU is started first, and the firmware is read from address 0 of the FLASH After the program, the MCU can run the program. Specifically, the MCU, as the main chip, runs its own boot program solidified into the chip. After the boot program runs, it reads its own firmware program from the 0 address of the FLASH. After the program i...

Embodiment 2

[0037] image 3 A schematic diagram of the actual connection structure and the level signal therein is shown when an actual camera chip is connected to the FPGA.

[0038] What is shown in this embodiment is the MER-500-14U3X camera independently developed by Daheng Image, which adopts the dual-chip architecture of CYUSB3014 and Spartan-6, and its startup and loading process adopts the scheme described in the present invention. The hardware connection diagram is as follows image 3 As shown, in this embodiment, the pins of the start-up and running process are ingeniously time-division multiplexed, and the DIN pin is used as the input of the program loading data during start-up. During the running process, the CS_FPGA, MOSI, CLK , MISO (FPGA_DIN) four pins form the CYUSB3014-based SPI control interface, where FPGA_DIN changes direction to output. For the purpose of saving connections, in this embodiment, the connection of the DONE signal is cancelled, and instead the FPGA is co...

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Abstract

The invention discloses a dual chip loading method based on MCU and FPGA. The method is for dual chip loading of a system having a first chip, a second chip and a single firmware program storage device, the first chip and the second chip having clock and data communication connections therebetween, the first chip and the second chip being communicatively connected to the firmware program storage device. The loading method of the invention enables the read data to enter the MCU and the FPGA respectively, and the configuration timing can be configured successfully as long as the configuration timing of the FPGA is ensured. This loading scheme reduces the time to start the configuration and the dependency on memory size.

Description

technical field [0001] The invention relates to the field of electronics, in particular to a dual-chip loading method based on MCU and FPGA. Background technique [0002] In industrial applications, in order to ensure the stable and reliable operation of equipment, dual-chip control is often required. [0003] The loading program of the embedded main chip usually starts from the 0 address of FLASH, loads the data of the specified length into RAM, and then starts to run the program. For the boot loading of dual chips, there are usually two ways: Option 1, each main chip has a separate external FLASH, and each chip starts to read the program from the 0 address of its own FLASH; Option 2, select a chip as the boot Chip, when the chip program is running, the chip reads the program of another chip into the memory, and then configures and loads another chip. [0004] The disadvantage of the existing solution 1 is that the two FLASH chips increase the cost, increase the difficult...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F9/445
CPCG06F9/44521
Inventor 杨煦宋伟铭周中亚李润锋刘敏
Owner BEIJING DAHENG IMAGE VISION
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