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High-holding current ESD protection device

A high-maintenance, current technology, applied in the field of electronic science and technology, can solve problems such as increasing area and reducing robustness, and achieves the effect of improving robustness and avoiding latch-up

Active Publication Date: 2019-01-01
UNIV OF ELECTRONICS SCI & TECH OF CHINA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

That is: the need for latch-free operation will reduce the robustness, and if the ESD robustness of the latch-free device needs to be improved, the area needs to be increased

Method used

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  • High-holding current ESD protection device

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0031] Such as image 3 As shown, the device structure of this embodiment includes: a P-type substrate 00, a first N-type epitaxial layer 01 located above the P-type substrate 00, and a first PWELL region located on the upper left side of the first N-type epitaxial layer 01. 201. The first P+ contact region 21 located above the interior of the first PWELL region 201, the first N+ contact region 11 located above the interior of the first PWELL region 201; wherein the first P+ contact region 21 is located to the left of the first N+ contact region 11 side; the second PWELL region 202 located on the right side above the inside of the first N-type epitaxial layer 01, and the second P+ contact region 22 located above the inside of the second PWELL region 202; located above the first N-type epitaxial layer 01 and not connected to the second A PWELL region 201, the second N+ contact region 12 in contact with the second PWELL region 202; the first N+ contact region 11 and the first P+...

Embodiment 2

[0040] Such as Figure 4 As shown, the device structure of this embodiment differs from that of Embodiment 1 in that: a NWELL region 10 is located between the first PWELL region 201 and the second PWELL region 202 , and the second N+ contact region 12 is located above the interior of the NWELL region 10 .

Embodiment 3

[0042] Such as Figure 5 As shown, the main difference between this embodiment and Embodiment 2 is that: a TOP region 23 is provided above the second PWELL region 202 . Wherein, the TOP region 23 is P-type doped, or N-type doped.

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PUM

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Abstract

The present invention provides a high-holding current ESD (ElectroStatic Discharge) protection device. The device comprises a P-type substrate, a first N-type epitaxial layer, a first PWELL region, afirst P+ contact region, a first N+ contact region, a second PWELL region, a second P+ contact region and a second N+ contact region; the first N+ contact region and the first P+ contact region form ametal cathode through metal short connection; the second P+ contact region and the second N+ contact region form a metal anode through metal short connection. The high-holding current ESD protectiondevice regulates the concentration and the length of the second PWELL region to regulate the holding current so as to avoid that the device generates latch-up, allow the device IV curve to show multi-time snapback features and improve the robustness of the device in the ESD pulse current.

Description

technical field [0001] The invention belongs to the field of electronic science and technology, and mainly relates to the electrostatic discharge (ElectroStatic Discharge, referred to as ESD) protection technology on the integrated circuit chip, specifically relates to a class of devices with low power consumption and strong latch-up resistance. ) capability, ESD protection devices for high-voltage integrated circuits. Background technique [0002] ESD stands for Electrostatic Discharge, which is a common phenomenon in nature. ESD exists in every corner of people's daily life. But it is such a common electrical phenomenon that is a fatal threat to sophisticated integrated circuits. However, for chips that have been packaged, each power supply / input / output pin becomes a channel for pulse currents such as human body model (HBM), machine model (MM), and human body metal model (HMM). Strong ESD pulses will not only cause hard failure of the chip, but also induce various effec...

Claims

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Application Information

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IPC IPC(8): H01L27/02
CPCH01L27/0296
Inventor 乔明肖家木齐钊梁龙飞何林蓉梁旦业张波
Owner UNIV OF ELECTRONICS SCI & TECH OF CHINA