Semiconductor device and its production method

A manufacturing method and semiconductor technology, applied in the direction of semiconductor/solid-state device manufacturing, semiconductor devices, electric solid-state devices, etc., can solve the problem of increasing the size of semiconductor devices

Inactive Publication Date: 2012-01-11
SHARP KK
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Accordingly, the size of semiconductor devices is likely to increase

Method used

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  • Semiconductor device and its production method
  • Semiconductor device and its production method
  • Semiconductor device and its production method

Examples

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no. 1 example ）

[0057] will refer to Figures 1 to 5 A semiconductor device according to a first embodiment of the present invention is described. figure 1 is a cross-sectional view of the semiconductor device according to the present embodiment. figure 2 is a circuit diagram for describing a diode of the semiconductor device according to the present embodiment. Figures 3 to 5 is a view showing a manufacturing process of the semiconductor device according to the present embodiment.

[0058] Such as figure 1 As shown, the semiconductor device according to this embodiment includes a P-type semiconductor substrate 1, a P-type well region 4 formed on a part of the P-type semiconductor substrate 1, and a P-type well region 4 formed on another part of the P-type semiconductor substrate 1. And the N-type epitaxial layer 2 arranged adjacent to the P-type well region 4 and the N-type buried layer 6 formed under the N-type epitaxial layer 2 .

[0059] P-type semiconductor substrate 1 has, for e...

no. 2 example ）

[0098] will now refer to Figures 6 to 12 A semiconductor device according to a second embodiment of the present invention is described. Figure 6 is a cross-sectional view of the semiconductor device according to the second embodiment. Figures 7 to 12 is a view showing a manufacturing process of the semiconductor device according to the second embodiment.

[0099] Such as Figure 6 As shown, the semiconductor device according to the second embodiment is similar to the semiconductor device in the first embodiment, which includes a P-type semiconductor substrate 1, a P-type well region 4, an N-type epitaxial layer 2, an N-type buried layer 6, and a deep The trench 8 also includes a PMOS transistor formed on the N-type epitaxial layer 2 and an NMOS transistor formed on the P-type well 14 . The semiconductor device according to the second embodiment further includes an N-type well region 3 and a second P-type well region 5 via a shallow trench 7A, wherein a PMOS low breakdown...

no. 1 example 1

[0112] As in the first embodiment, first prepare to have 1×10 17 / cm 3 P-type semiconductor substrate 1 with an impurity concentration of .

[0113] Then, if Figure 7 As shown in (a), grow on P-type semiconductor substrate 1 with 4×10 16 / cm 3 N-type epitaxial layer 2 with impurity concentration and thickness of 3 μm. The process is the same as that described in the first example image 3 The process in (a) is the same.

[0114] Then, if Figure 7 As shown in (b), a shallow trench 7 is formed on the N-type epitaxial layer 2 by a known process, and a deep trench 8 is formed on the N-type epitaxial layer 2 and the P-type semiconductor substrate 1 . This process is also the same as that in the first embodiment. However, in the second embodiment, shallow trench 7A is formed at the boundary between high breakdown voltage transistor regions 50 and 51 and a region where low breakdown voltage transistors are formed (hereinafter referred to as low breakdown voltage transistor ...

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Abstract

The invention provides a semiconductor device and its production method. The semiconductor device in the invention includes: a semiconductor substrate of a first conductive type; a first well region of the first conductive type formed in the semiconductor substrate; an epitaxial region of a second conductive type formed in the semiconductor substrate and arranged in a region adjacent to the first well region; a buried region of the second conductive type that is formed in a region at a lower part of the epitaxial region and that has an impurity concentration higher than that of the epitaxial region; a trench formed at boundaries between the first well region and the epitaxial region, and between the first well region and the buried region; a first semiconductor element that is formed on the first well; and a second semiconductor element that is formed on the epitaxial region.

Description

[0001] Cross References to Related Applications [0002] This application is related to Japanese Patent Application No. 2010-155928 filed on Jul. 8, 2010, the priority of which is claimed and the entire contents of which are hereby incorporated by reference. technical field [0003] The present invention relates to semiconductor devices and methods of manufacturing the same, and particularly to CMOS transistors and methods of manufacturing the same. Background technique [0004] The CMOS (Complementary MOS) structure is a structure in which N-channel MOS transistors and P-channel MOS transistors are integrated at the same time. This structure is widely used in many semiconductor device circuits. For example, this structure is applied even to circuits requiring a high breakdown voltage such as a liquid crystal driver. [0005] However, it is known that in a CMOS structure, a parasitic bipolar transistor is formed between adjacent regions and due to the behavior of this tran...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/092H01L29/06H01L21/8238
CPCH01L27/0921
Inventor 疋田智之桥本尚义
Owner SHARP KK
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