A storage synchronization method of multi-channel acquisition system based on multi-FPGA

A multi-channel acquisition and system storage technology, which is applied in the field of high-speed acquisition system storage synchronization, can solve complex synchronization problems, achieve the effect of eliminating trigger shaking and saving pin resources

Active Publication Date: 2019-01-29
UNIV OF ELECTRONICS SCI & TECH OF CHINA
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Problems solved by technology

Under the framework of multi-ADC+multi-FPGA, the synchronization of storage becomes very complicated due to the increase of interconnection lines between FPGAs. big difficulty

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  • A storage synchronization method of multi-channel acquisition system based on multi-FPGA
  • A storage synchronization method of multi-channel acquisition system based on multi-FPGA
  • A storage synchronization method of multi-channel acquisition system based on multi-FPGA

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Embodiment

[0047]After the analog signal is quantized into a digital signal by the ADC, the waveform data needs to be stored. Usually, the FIFO (first-in-first-out) resource inside the FPGA is used as the buffer area for collecting data, and the read and write of the FIFO can be phased between different FPGAs. The relationship is random, so when the waveform is stored, due to the inconsistency of the read and write enable, the FIFO storage between different FPGAs is not synchronized.

[0048] The synchronized ADC sampling data is sent to the FPGA, and the asynchronous opening time of the FIFO write enable between different FPGAs will lead to asynchronous waveform storage.

[0049] figure 1 Among them, DCLK is the data clock after ADC synchronization, ADC1_DATA and ADC2_DATA are the sampling data after two ADCs are synchronized respectively, FPGA1_FIFO_WEN and FPGA2_FIFO_WEN are FIFO write enable in two FPGAs respectively, determined by figure 1 It can be seen that the synchronized sampl...

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Abstract

The invention discloses a storage synchronization method of a multi-channel acquisition system with multi-FPGA, the interconnection relationship between FPGAs is established by using the interconnection lines between FPGAs. According to the trigger source, the master-slave trigger property is selected, and the master FPGA synchronously collects the write enable of the slave FPGA, the digital trigger precise positioning, and the digital trigger positioning value synchronously realizes the storage, read and write synchronization of the multi-FPGA multi-channel acquisition system.

Description

technical field [0001] The invention belongs to the technical field of high-speed acquisition system storage synchronization, and more specifically relates to a method for storage synchronization of a multi-FPGA multi-channel acquisition system. Background technique [0002] Multi-channel synchronization is a very important indicator in a multi-channel acquisition system. In a multi-channel acquisition system, especially in a test system, it is not only required to analyze the characteristics of the channel input signal itself, but also to analyze the correlation of the signals between channels, which requires synchronization of the acquisition system. [0003] The rapid development of electronic technology has put forward higher requirements for the indicators of the acquisition system. The traditional single-ADC+single-FPGA structure is far from meeting the sampling rate requirements of high-speed acquisition systems. Although the multi-ADC+single-FPGA architecture solves...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F13/40G05B19/042
CPCG05B19/0423G06F13/405G06F13/4068
Inventor 杨扩军赵禹张沁川叶芃邱渡裕
Owner UNIV OF ELECTRONICS SCI & TECH OF CHINA
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