59results about How to "Save pin resources" patented technology

An embodiment of the invention provides a data transmission method, device and system of a data storage system. The data transmission method includes: a central processing unit interface configured on data transmission equipment receives a data transmission instruction transmitted by a central processing unit so as to obtain target storage media corresponding to address precedence codes, the data transmission instruction is transmitted to the target storage media through target storage medium interfaces connected with the target storage media, and the data transmission instruction is executed in the target storage media, wherein each address precedence code corresponds to one of at least two storage media of different types. The method has the advantages that the central processing unit can be connected with different storage media by being connected with one central processing unit interface disposed on the data transmission equipment, the pin resources of the central processing unit are saved, and the utilization rate of the pin resources of the central processing unit is increased.

The invention relates to a circuit for accessing a chip test mode and a control method of the circuit. The circuit comprises a power-on reset logic module and a counting decoding logic module, an existing chip pin is reused, the counting decoding logic module based on one-hot encoding counting is designed to access and switch various test modes, pin sources of a chip are saved, test efficiency ofthe chip is improved, chip test is in a scan chain test mode when clock jump is driven, and the test coverage rate of a scan chain can be increased.

The invention provides a power supply control device and a power supply control system. The device comprises a first input node, a first comparator, a second comparator, a controlled source, an amplifier, an or logic gate circuit, a delay circuit, a first NAND logic gate circuit and a second NAND logic gate circuit. By the power supply control device and the power supply control system, the problem that a power supply system in the related technology occupies much pin resources is solved; the pin resources and the system cost are saved; and the utilization rate of pins is improved.

The invention relates to a current and effect stabilizing control circuit chip and a safe control electric appliance of the control circuit chip. The current and effect stabilizing control circuit chip and the safe control electric appliance adopt the technical scheme that two parallel and complementary unit circuits are adopted for forming the current and effect stabilizing control circuit chip, wherein the input end of an isolation switch arranged in each unit circuit is connected with an amplifier; the output end of the isolation switch arranged in each unit circuit is connected with a bottom supporting type safe control circuit; weak sensing signals are amplified and are then transmitted to the bottom supporting type safe control circuit to be processed by the isolation switch; the strong sensing signals can be directly sent to the bottom supporting type safe control circuit to be processed directly from the level input end; each bottom supporting type safe control circuit has the bottom supporting protection and limit exceeding safety control function; in addition, the two bottom supporting type safe control circuits are mutually locked; if the inputs of the two unit circuits are used for parallelly detecting the sensing signals and the outputs of the two unit circuits are used for serially connecting a peripheral driving executing circuit, and the capability of comprehensively preventing the fault control loss is realized, so that when the current and effect stabilizing control circuit chip is applied to safety protection and test control circuits for the temperature, the pressure, the water level, the timing and the like, the safety performance can be improved, the control loss accident can be avoided, and the purposes are wide.

The invention provides an ID configuration method of a series circuit, the series circuit comprises a chipset, and the chipset comprises a plurality of chips which are sequentially connected in series, wherein the chip located at the head end of the chipset is connected to a power supply end through an input pin of the chip, an input pin of the ith chip in the chipset is connected to an output pinof the (i-1) th chip, and i is an integer greater than 1; the method comprises the steps that S1, the chipset receives an ID configuration package; s2, configuring a configuration ID in the ID configuration packet by a chip meeting a preset configuration condition in the chipset through a register of the chip; and S3, executing the steps S1 to S2 again, so that the next chip meeting the preset configuration condition in the chipset is subjected to ID configuration. The invention further provides a control terminal. The invention further provides a control terminal applying the method and a computer readable storage medium. Compared with the prior art, pin resources of the chip are saved, the ID configuration range is expanded, and the types of the configured IDs are rich.

The invention relates to the relevant technical field of capacitor balancing, and in particular relates to a multi-parallel-and-serial super capacitor system balancing method. A super capacitor is formed by the combination of a plurality of monomer capacitors in a serial and/or parallel mode. The system comprises the super capacitor and a controller; a discharge resistor is connected in parallel to two ends of each monomer; each discharge resistor is connected with a switch module in series; and each switch module is connected with the controller, and is conducted or stopped by the control of the controller, thus the connection and disconnection of a discharge loop are controlled. According to the invention, by designing a passive balancing circuit, an appropriate balanced strategy is matched, the integral performance of a capacitor group is improved, the capacitor using rate is improved, and the service life of the capacitor group is prolonged. The balancing scheme provided by the invention is simple and reliable, and is high in interference prevention capability; and by means of a serial communication module, pin resources of the controller are saved greatly.

The invention particularly relates to an automatic allocation method for blade server management internal network IPs. According to the automatic allocation method for the blade server management internal network IPs, each calculation blade in a blade server is configured with a CPLD (Complex Programmable Logic Device) chip; UART (Universal Asynchronous Receiver/Transmitter ) interfaces of the CPLD chips are connected with a backboard; a UART RX end of a first calculation blade is hung; a UART TX end of the first calculation blade is connected with the RART RX end of a second calculation blade, the rest can be done in the same manner, and the UART TX end of an nth calculation blade is connected with the UART RX end of an n+1th calculation blade, until the final calculation blade is finished; and the UART TX end of the final calculation blade is hung. According to the automatic distribution method for the blade server management internal network IPs, only three pins are connected with the backboard and a demand of allocating different IP addresses to dozens of blades can be realized; the method is stable and reliable; BMC IO resources and backboard connector pin resources can be saved; and the method is superior to the prior art and is applicable to popularization and application.

The present invention provides communication device, test system and test method thereof, the communication device comprising: a baseband chip, and a target test chip, an upper processing module on the target test chip, at least one data receiving and transmitting interface and a data processing module thereof, a first switch, a second switch and a test control module integrated in the baseband chip, wherein the first switch is used for achieving connection between the target test chip and the data receiving and transmitting interface or the upper processing module; the second switch is used for achieving connection between the data receiving and transmitting interface and the data processing module or the target test chip; the test control module is used for controlling the first and second switches to connect the data receiving and transmitting interface with the target test chip, so that the communication device is suitable for testing the target test chip. The technical solution of the present invention does not need additional test pins while testing the target chip, saves resources for the communication device and reduces cost.

The embodiment of the invention relates to the technical field of communication, and discloses a hardware module testing method and system, electronic equipment and a storage medium. The hardware module test method comprises the steps of obtaining pin information of a to-be-tested hardware module; acquiring information of a micro control unit (MCU) for testing the hardware module to be tested, wherein the information of the MCU at least comprises pin information of the MCU; obtaining a test configuration file according to the pin information of the hardware module to be tested and the pin information of the MCU; and obtaining a test result of the to-be-tested hardware module according to the test configuration file. According to the hardware module test method provided by the embodiment ofthe invention, complex instruments and meters are not needed, the test cost can be reduced, the test process of the hardware module is flexibly configured, and the operability and expandability of the test process are greatly improved.

The invention discloses a pan-tilt motor limiting method and device, a pan-tilt camera and a storage medium. The method comprises the following steps: acquiring a sound signal acquired by a microphone; extracting feature information of the sound signal to obtain first feature information; comparing the first feature information with pre-stored second feature information, wherein the second featureinformation is feature information of impact sound generated when the motor and/or the holder impacts the limiting structural member; and if the first feature information is consistent with the second feature information, stopping sending a first rotation instruction to the motor, the first rotation instruction being used for controlling the motor to rotate. In this way, impact noise can be reduced.

The invention relates to the field of embedded chips, and provides a synchronous serial bus multiplexing method and device, a terminal and a non-temporary computer readable storage medium. The invention aims to reduce the number of consumed pins when a main chip is connected with VGA and IC interfaces. The method comprises the following steps that an input/output pin driven by a multiplex drivingmodule is applied for as a pin, corresponding to a synchronous serial bus, of a main chip; the multiplexing driving module judges a driving module corresponding to a current application; if the driving module corresponding to the current application is a driving module of hardware equipment corresponding to a first interface, the input/output pin driven by the multiplexing driving module is applied to the first interface; and if the driving module corresponding to the current application is a driving module of hardware equipment corresponding to a second interface, the input/output pin drivenby the multiplexing driving module is applied to the second interface. According to the invention, pin resources of the main chip are saved, convenience is provided for adding other more functions tothe main chip, and multiplexing of the synchronous serial bus is realized on a software level.

The embodiment of the invention provides a semiconductor chip and a control method thereof. The semiconductor chip includes: a first pin; a second pin; a non-volatile memory; a programming module configured to program the calibration data to the non-volatile memory upon receiving a programming command; and a controller which is coupled to the first pin, the second pin and the programming module, and is configured to enable the semiconductor chip to enter a calibration mode if a command received from an upper computer through the first pin is a preset byte when the semiconductor chip is poweredon, and enable the semiconductor chip to enter a normal working mode if the command is not the preset byte; in the calibration mode, the internal clock frequency is output through the first pin; calibration data is received via the first pin; a program enable command is received via the first pin; and the programming module is caused to carry out programming using the calibration data based on the program enable command. The semiconductor chip described herein may utilize two pins to achieve a variety of functions.

The invention provides a data transmission method and device, the method is applied to a main control board in routing equipment, an LVDS bus is arranged between the main control board and any one line card board in the routing equipment, and the method comprises the following steps: when it is detected that the LVDS bus has an idle frame and target data needs to be read/written on any one line card board, sending the idle frame to the LVDS bus; sending the start frame to the line card board through the LVDS bus, so that the line card board stops sending the idle frame when receiving the start frame; and after the start frame is sent, a data request frame is sent to the line card board through the LVDS bus, so that the line card board executes related read/write operation on the basis of receiving the data request frame. According to the routing equipment, data transmission between the main control board and the line card board in the routing equipment is realized through the LVDS bus, less pin resources can be occupied, and thus the space of a PCB (Printed Circuit Board) is saved.

The invention provides an electric locomotive traction controller state feedback device and a system. the electric locomotive traction controller state feedback device comprises a signal converter and a signal processor, wherein the signal converter comprises at least two ways of signal input ends and one way of signal output end; the at least two ways of signal input ends is connected with a traction converter cabinet feedback device of the electric locomotive; the one way of signal output end is connected with the signal processor; the signal converter is used for converting digital state feedback signals inputted by the at least two ways of signal input ends respectively to a way of analog output signals, and the way of analog output signals is outputted to the signal processor; and the signal processor is used for carrying out signal analysis on the way of analog output signals to obtain digital state feedback signals. According to the electric locomotive traction controller state feedback device provided by the invention, the resource utilization rate of a core control chip can be enhanced.

The invention discloses a multifunctional infrared electric energy meter. The multifunctional infrared electric energy meter comprises a single chip microcomputer and an infrared transmitting tube andan infrared receiving tube connected to the single chip microcomputer. The single chip microcomputer receives a detection instruction of an external electric energy meter detecting device through theinfrared receiving tube. The detection instruction comprises a communication command, a measurement command, and a clock command. The single chip microcomputer controls the infrared transmitting tubeto output a signal to be detected according to the detecting instruction. The electric energy meter detecting device detects the electric energy meter according to the signal to be detected outputtedby the infrared transmitting tube. The signal to be detected comprises an infrared communication signal, a measurement error signal, and a clock error signal. The multifunctional infrared electric energy meter has advantages that the IP54 waterproof rating of the electric energy meter is realized at a low cost, the antistatic level of the electric energy meter is improved, and the overall productquality is improved; and the production efficiency is improved, the production cost is reduced by a non-contact detection method, the automation level of the electric energy meter production is improved, and the quality of electric energy meter products is improved.

The invention relates to a connection method for a digital sensor array. Multiple digital sensors adopt array distribution, rows and columns of an array are clock lines or data lines, a clock line SCLof each sensor in the array is connected to a clock line SCLi of the array, and i is equal to 1-M; a data input/output line SDA of each sensor in the array is connected to a data line SDAj of the array, and j is equal to 1-N; an IO pin of a micro controller is connected to the clock line and the data line of the sensor array; and the micro controller drives the clock line of the digital sensor array and reads in data of all the sensors in the array by virtue of the data line of the array.