11results about How to "Save pin resources" patented technology

The utility model provides a serial port multiplexing circuit based on RS485 and RS232, and an electronic device, a serial port sending end of a main control module is connected with a receiving end of an RS232 driving circuit, a differential signal end of the RS232 driving circuit is connected with a change-over switch, and an output end of the RS232 driving circuit is connected with a first input end of a logic AND gate circuit; the serial port sending end of the main control module is connected with the logic NOT gate circuit, and the logic NOT gate circuit is connected with the enabling end of the RS485 driving circuit; the receiving end of the RS485 driving circuit is connected with the grounding end, and the differential signal end of the RS485 driving circuit is connected with the change-over switch; the differential signal end of the RS485 drive circuit is provided with a pull-up resistor and a pull-down resistor. The change-over switch is connected with the connecting terminal; the output end of the logic AND gate circuit is connected with the serial port receiving end of the master control module. According to the utility model, the use of pin resources of main control equipment can be reduced.

The utility model relates to the technical field of temperature and humidity monitoring, and discloses a temperature and humidity conversion unibus circuit, which comprises a temperature and humidity sensor chip U1, a 1-Wire bus interface chip U2, a 100nF filter capacitor C1, a 2uF filter capacitor C2 and a Schottky diode D1, the IO pin 1 of the 1-Wire bus interface chip U2 is connected with a DQ line, the DQ line is a data signal line connected with a bus, and the IO pin 2 of the 1-Wire bus interface chip U2 is connected with the Schottky diode D1. And the anode of the Schottky diode D1 is connected with a DQ line, the cathode of the Schottky diode D1 is connected with VDD, and the Schottky diode D1 is used for providing reverse voltage protection for a pin IO of the 1-Wire bus interface chip U2. According to the technical scheme of the utility model, DS28EA00U + Tamp is adopted. The R1-Wire bus interface chip U2 and the IC bus of the SHT30-DIS-B temperature and humidity sensor chip U1 are multiplexed, a set of communication line does not need to be independently arranged for each chip, and the design of a power supply loop is simplified.

The invention relates to a read-write method and a read-write system for an MCU embedded memory, which are applied to the technical field of read-write, and the read-write method comprises the following steps: an upper computer sends an operation instruction, and the operation instruction comprises a read operation instruction or a write operation instruction; the simulator is used for receiving the operation instruction and transmitting the operation instruction to the MCU chip; and the emulator is used for configuring the MCU chip and controlling the MCU chip to execute an operation corresponding to the operation instruction. The method has the technical effects that data downloading and backward reading can be carried out on the MCU embedded memory of Manchester encoding single-wire communication, and the data can be verified after backward reading, so that the MCU can normally run a program, the use of chip pin resources is reduced, and the data reading and writing efficiency is improved.

The present invention relates to the field of chip design, and specifically discloses a chip pin multiplexing circuit and method. By setting a general function control unit, a special function control unit and other function modules, the multiplexed pins can be used as normal functions at any time; when a special function is needed, such as an online debugging function, after connecting a hardware debugger, it can be switched to the debugging function, and the running code will not affect the debugging signal and function; after the debugging is completed, after removing the hardware debugger, it can be restored to the normal function. The beneficial effect is: the chip pin multiplexing is realized, which not only saves pin resources, but also does not affect the use of normal functions.

The invention relates to the technical field of information interaction transmission, and discloses an FPGA satellite signal management information inter-chip interaction system which comprises a plurality of FPGA chips which are sequentially connected through double wires from top to bottom. Wherein the FPGA chip at the upper part comprises a data conversion module and a data receiving management module; and the FPGA chip at the bottom comprises a data receiving management module and a data framing module. According to the invention, the transmitted digital information is represented in a pulse signal mode, the stability and accuracy of data transmission can be effectively improved, and the high efficiency of data information is also satisfied through effective management of data.

The invention discloses a clock-free four-port multi-address wafer acceptance test structure and a test method thereof. A test structure composed of four ports, N triggers and N layers of tree-shaped gating circuits successfully breaks through the limitation of a traditional test structure on the basis that an existing WAT test machine table and a test needle card do not need to be changed at all. Through cooperative work of the signal port, the beat port, the power supply port and the grounding port with the test machine and ingenious combination of the trigger and the tree-shaped gating circuit, a large number (dozens, hundreds and even thousands) of test structures can be tested very efficiently. Time waste and resource consumption caused by repeated testing of the TestKey are completely avoided, and testing efficiency and flexibility are greatly improved.

The embodiment of the invention provides a chip internal signal sampling method, a controller, equipment and a system. The chip internal signal sampling method has the following beneficial effects that a chip internal signal sequence is received; if the idle identifier is received, outputting a first level according to a time length T0; if the logic coding signal bearing the logic information 0 is received, the second level is output according to the time length T1, and the first level is output according to the time length T2; if the logic coding signal bearing the logic information 1 is received, the second level is output according to the time length T2, and the first level is output according to the time length T1; the first level and / or the second level are / is output to off-chip acquisition equipment through a single pin so as to acquire internal signals of the chip according to the time length T3. According to the invention, serial output and acquisition of signals are realized by using a single pin, a large number of pins are not required to be used for connecting an on-chip memory, pin resources are saved, dependence on internal storage is eliminated, and the integrity of the acquired signals is improved.

The application provides a multi-spi flash redundancy booting firmware method, and specifically as follows: an SPI bus on an MCU is connected in parallel with multiple SPI FLASHes, and then a GPIO pin of the MCU is used as CS0 and CS1 to be connected to CS pins of the SPI FLASHes respectively; an SPI FLASH to be measured is selected, and then an Xth data block in the SPI FLASH to be measured and a CRC check code of the Xth data block are read; a CRC check code corresponding to the read Xth data block is calculated, and is compared with the CRC check code stored in the SPI FLASH to be measured; if the CRC check code corresponding to the read Xth data block is equal to the CRC check code stored in the SPI FLASH to be measured, it is indicated that the check is passed, and the data is correct; if the CRC check code corresponding to the read Xth data block is not equal to the CRC check code stored in the SPI FLASH to be measured, it is indicated that the data is incorrect, and the next SPI FLASH needs to be continuously read, and the detection is sequentially performed. The application improves the reliability of the system, and is beneficial to long-time stable operation of the equipment.

The present invention relates to a temperature screening circuit, comprising comparators U1, U2, U3, multi-stage electric control switches SW1, SW2 and two temperature collection points for collecting the voltage output by a temperature sensing device, wherein one temperature collection point is respectively connected to the same direction input end of the comparator U1 and the reverse direction input end of the comparator U2, and the other temperature collection point is respectively connected to the reverse direction input end of the comparator U1 and the same direction input end of the comparator U2; the output end of the comparator U3 is connected to the controlled end of the multi-stage electric control switch SW2, the output ends of the comparators U1 and U2 are respectively connected to the two connection ends of the multi-stage electric control switch SW2, the output end of the multi-stage electric control switch SW2 is connected to the controlled end of the multi-stage electric control switch SW1, and the two temperature collection points are respectively connected to the two connection ends of the multi-stage electric control switch SW1; if the voltage output by the temperature sensing device is negatively correlated with the temperature, the reverse direction input end of the comparator U3 is used to receive the reference voltage, and the same direction input end is connected to the temperature collection point, otherwise the connection method of the input end of the comparator U3 is opposite.

This disclosure provides a chip testing apparatus, a chip testing system, and a chip testing method. The chip testing apparatus includes: a chip under test (TBT) with multiple input / output pins, wherein the input / output pins output test output signals during the testing process of the TTB; and a logic operation circuit for performing logical operations on the multiple test output signals output from the multiple input / output pins to obtain the test result of the TTB, and outputting the test result through a unified output pin. This chip testing apparatus eliminates the need for multiple test output pins, allowing for the output of a unified test result from a single pin. This reduces the pin resources required for the test output pins, thus saving pin resources associated with the test result of the TTB and improving resource utilization.

The invention relates to the technical field of over-temperature and over-voltage protection circuits, and discloses an over-temperature and over-voltage protection circuit, a circuit board, a switching power supply and electronic equipment. The over-temperature and over-voltage protection circuit comprises a trigger circuit, a controller, a temperature detection circuit and a voltage sampling circuit, wherein the temperature detection circuit generates a temperature detection signal at the second node according to the environment temperature, so that the trigger circuit triggers the controller to execute over-temperature protection operation. The voltage sampling circuit generates a voltage detection signal at the third node according to the external voltage, so that the trigger circuit triggers the controller to execute overvoltage protection operation. The temperature detection circuit and the voltage sampling circuit share the trigger circuit, so that the integration level of the over-temperature and over-voltage protection circuit is high. The detection results of the temperature detection circuit and the voltage sampling circuit are finally represented by the voltage of the first node, the controller only needs to open up a control pin to be electrically connected to the first node, and there is no need to open up an additional control pin for two functions, so that precious pin resources can be saved.