39results about How to "Save PCB space" patented technology

The invention discloses a module for starting multiple user programs by a single Flash. The module is characterized by comprising one programmable device and one FLASH chip connected with the programmable device, wherein multiple user program storage regions and one public program storage region are divided in the FLASH chip, each user program storage region stores one corresponding user program, and the public program storage region stores one corresponding EEPROM (Electrically Erasable Programmable Read-Only Memory) program; the programmable device can accept the access of multiple CPUs (Central Processing Units) and one FPGA (Field Programmable Gate Array) in parallel, thereby realizing that the public program storage region in the FLASH chip corresponds to the FPGA, and each user program storage region respectively corresponds to one CPU; and a bus switching module is designed in the programmable device, and the bus switching module can orderly transmit the user programs in the user program storage regions of the FLASH chip to the corresponding CPUs and transmit the EEPROM program to the corresponding FPGA.

The invention discloses a method for remotely upgrading an FPGA (Field Programmable Gate Array) program based on a ZYNQ chip. The related main devices comprise a zynq chip, an FPGA chip, a QSPI (QuadSerial Peripheral Interface) storage chip, an EMMC (Enhanced Media Card) storage chip and a DDR3 (Double Data Rate 3) memory chip. Program upgrading, the PC is connected with the ZYNQ through the Ethernet; the program is transmitted from the PC end to the ZYNQ external EMMC storage chip for storage; Each time the device is powered on, The application program in the PS of the ZYNQ moves the FPGA program in the EMMC storage chip to the PL part of the ZYNQ, the transmission logic of the SelectMap is compiled in the PL, and the program can be transmitted to the FPGA from the PL part through a SelectMap method so as to be started. The data migration from the EMMC storage chip to the PL is realized in the DDR3 externally matched with the ZYNQ after the mapping from the physical address to the virtual address is completed. According to the method, remote upgrading of the equipment can be realized.

The invention discloses a four-axis unmanned aerial vehicle, including a frame, a motor, a propeller, a battery and a flight control board, and the flight control board includes: an attitude sensor group for detecting attitude data of the four-axis unmanned aerial vehicle; a power supply The circuit distributes the power provided by the battery according to the different requirements of each module on the flight control board; the motor drive circuit is used to drive the motor to rotate; the main control MCU, including the controller and wireless transceiver, is used to obtain The attitude data of the four-axis drone is converted into the actual attitude and position information of the four-axis drone, and with the remote control information sent by the wireless transceiver, the four motor speeds of the four-axis drone are controlled through the motor drive circuit; the battery power detection module , located between the battery and the main control MCU. The main control MCU of the present invention integrates the controller and the wireless transceiver into a single chip, which not only improves the integration degree of the flight control board, saves PCB space, but also improves the stability and robustness of the system.

The invention relates to a data processing method, a security chip device and an embedded system, belongs to the technical field of computers, and solves the problems of low data processing rate and incapability of adapting to encryption and decryption algorithms with large calculated amount in the prior art. The method comprises the following steps: S1, storing a first data stream in a first RAM;S2, storing the second data stream in a second RAM, processing the first data stream through an algorithm unit, and storing the processed first data stream in a first RAM; S3, outputting the processed first data stream to an upper computer, processing a second data stream through an algorithm unit, and storing the processed second data stream in a second RAM; and S4, outputting the processed second data stream to an upper computer, wherein T is a data processing period. Within the same T, the number of data processing is increased, the utilization rate of algorithm units is improved, and therefore the working efficiency is improved.

The invention discloses a design method for saving space by using a high-density connector wafer. The method comprises: S1, selecting driver chips with different drive capabilities based on combination of performance requirements of a high-speed link channel and a cost control requirement; S2, placing the driver chips on a connector; and S3, opening driving of a long link and closing driving of a short link are realized by using software according to link situations. Compared with the prior art, the method disclosed by the invention has the following beneficial effects: because the drivers are arranged on the connector wafer, the integration of the high-speed connector is improved; the driver chip space on the single board can be saved, so that the space is left for the layout and wiring of the single board; and the method is simple and is easy to use and the operability is high, so that the method is easy to implement in design and manufacturing.

The invention provides a dynamic font library optimization method based on a single-chip microcomputer, and relates to the technical field of single-chip microcomputers, and the method comprises the steps of enabling the single-chip microcomputer to be connected with an upper computer through a serial port, enabling a user to input a to-be-displayed target character through a man-machine interaction interface of an upper computer development system, and uploading and storing the to-be-displayed target character into the upper computer; enabling the upper computer to call a built-in dot matrixlibrary to encode the target character to form a first code, and storing the first code; correcting the original data model in the upper computer by adopting a classification algorithm and taking thefirst code as training data to obtain a new data model, and obtaining a code instruction and an information code through the new data model; and enabling the single-chip microcomputer to download andcall the code instruction and the information code, and control the LED dot matrix according to the information code. The problems that in the prior art, a single-chip microcomputer excessively depends on a specific word stock chip in LED dot matrix control, so that cost is high, use is not flexible, and information processing efficiency is low are solved.

The invention involves a photoelectric module component that can be inserted into the DWDM system and can be disassembled from the system.This component includes a photoelectric module (1) with multiple horizontal grooves (6) and multiple vertical slots (7). The groove and slot enable this optoelectronics module to insertLocated on multiple protrusions on the module installation device.The invention also integrates the EMI shielding function inside the component.

The invention discloses a control device for power supply voltage of a mainboard and a server. According to the scheme, the control device comprises a first power connector, a processor and N controllable switch modules which are arranged on the mainboard, the N controllable switch modules share the first power supply connector, and the processor controls the controllable switch module corresponding to the board card to be switched on when determining the board card inserted into the first power supply connector so as to provide corresponding power supply voltage for the board card. Compared with the prior art, the device has the advantages that the power connectors on the mainboard are shared when the mainboard supplies power to board cards with different power supply voltage requirements, the number of the power connectors on the mainboard, the cost consumed by more power connectors and the PCB space, occupied by the power connectors, of the mainboard are reduced, and the power density of a server where the mainboard is located is improved; Meanwhile, the probability of wrong connection between the board card and the power supply connector on the mainboard is reduced, so that the probability that the board card cannot work normally or even is burnt down is reduced.

The invention provides an antenna group and a communication device. The antenna group comprises neutralizing lines, a first antenna unit and a second antenna unit; the neutralizing line comprises first stubs and second stubs which are independently arranged; the first stubs are connected with the first antenna unit, and the second stubs are connected with the second antenna unit; the first stubs and the second stubs distributed elements; and the distributed elements include distributed inductors and / or distributed capacitors. According to the antenna group, the sectional neutralizing lines are adopted, the gaps and the wires of the neutralizing lines form the distributed elements, so that traditional lumped elements can be replaced, the decoupling of the antenna is realized, and a better decoupling effect and more optimized antenna performance are further provided.

The invention discloses a full-bridge over-current protection circuit and a full-bridge over-current protection method. The full-bridge over-current protection circuit comprises a first gating module, a first comparator, a second gating module, a second comparator and a logic control module, wherein the first gating module multiplexes the first comparator, and can selectively judge whether over-current happens to two upper bridge arms or not; and the second gating module multiplexes the second comparator, and can selectively judge whether two lower bridge arms have overcurrent. Therefore, the use number of the comparators can be reduced to two, and the PCB space or the integrated chip area is greatly saved.

The invention discloses an intelligent greenhouse management system comprising an implementation terminal, a communication terminal and an application terminal; the implementation terminal comprises an Internet of Things gateway, a sensor terminal node, a control terminal node and an execution device, and the sensor terminal node comprises a temperature and humidity sensor, an illumination sensor and a human body infrared sensor; and the sensor terminal node is electrically connected with the Internet of Things gateway, another interface of the Internet of Things gateway is electrically connected with the control terminal node, the control terminal node is wirelessly connected with the execution device, the execution device comprises a greenhouse and a spraying crane assembly, and the communication terminal comprises a WIFI communication module, a cloud end and an Internet of Things cloud platform. The application terminal comprises a database, an alarm monitor and a remote control, one ends of the database, the alarm monitor and the remote control are wirelessly connected with the Internet of Things cloud platform, and the other ends of the database, the alarm monitor and the remote control are wirelessly connected with the user mobile terminal, so that the barriers of high workload and high time consumption of traditional agriculture are broken, the agricultural greenhouse is managed more efficiently and conveniently, and agriculture develops in a more intelligent and more accurate direction.

The invention discloses a power supply control system. The power supply control system comprises a group of POL (Point of Load) or PB (Power Block) power supplies, a digital power controller and one or more isolation power level converters connected in parallel and is characterized in that the group of POL or PB power supplies are used for supplying power to a load; the isolation power level converter takes charge of converting input voltage to bus voltage and is communicated with the digital power controller; the controller is arranged in the isolation power level converter; the digital power controller is used for monitoring the POL or PB in the system and monitoring according to the type of the isolation power level converter. The power supply control system can reduce the cost, saves PCB spaces of the isolation power level converter, improves the power density of the isolation power level converter, improves the light load efficiency and optimizes the efficiency of the overall system.

The invention provides a data transmission method and device, the method is applied to a main control board in routing equipment, an LVDS bus is arranged between the main control board and any one line card board in the routing equipment, and the method comprises the following steps: when it is detected that the LVDS bus has an idle frame and target data needs to be read / written on any one line card board, sending the idle frame to the LVDS bus; sending the start frame to the line card board through the LVDS bus, so that the line card board stops sending the idle frame when receiving the start frame; and after the start frame is sent, a data request frame is sent to the line card board through the LVDS bus, so that the line card board executes related read / write operation on the basis of receiving the data request frame. According to the routing equipment, data transmission between the main control board and the line card board in the routing equipment is realized through the LVDS bus, less pin resources can be occupied, and thus the space of a PCB (Printed Circuit Board) is saved.

The invention discloses an SD card system applied to a server mainboard and a design method and the SD card system. The SD card system comprises a USB signal gating module, an SD Controller and an SDcard slot, wherein the USB signal gating module at least comprises two input ends and one output end; and the output end of the USB signal gating module is connected with the SD Controller and the SDcard slot in sequence. The design method comprises the following steps of: setting the USB signal gating module on the server mainboard to ensure that USB signals are connected with the SD Controllerthrough the USB signal gating module; and selectively gating the USB signals by utilizing the USB signal gating module. Through structural design of the SD card system, the occupation of mainboard PCBspace can be greatly decreased, benefit is brought to improve the device density of the server mainboard, and benefit is brought to reduce the comprehensive cost of the SD card system.

The invention provides a differential line winding method. The differential line winding method comprises the following steps: associating a first line of a differential line with a first hole; associating a second line of the differential line with a second hole, and causing the second line to protrude toward a direction away from the first line, so that a differential signal is matched at equallength. The method disclosed by the invention breaks through the limitation of 3W2S, and can solve the equal length matching problem of the differential signal just by using a winding unit combined with a through hole without generating problems in terms of SI of the signal. By adoption of the method, the PCB space needed for equal length winding of the differential high-speed signal on a differential line main circuit can be effectively reduced.

A power MOSFET package is disclosed. The power MOSFET package includes a leadframe having first and second die pads insulated one from the other, the first die pad being coupled to a first drain lead and the second die pad being coupled to a second drain lead. A first MOSFET device has a drain contact coupled-to the first die pad, a gate contact coupled to a first gate lead, and a source contact coupled to the second die pad. A second MOSFET device has a drain contact coupled to the second die pad, a gate contact coupled to a second gate lead, and a source contact coupled to a source lead. An encapsulant substantially encapsulates the leadframe, the first and second MOSFET devices and portions of the first and second gate leads, the first and second drain leads, and the source lead.

The invention discloses a lead frame, including a first lead frame and a bridge frame, the first lead frame includes a first chip seat, a plurality of first connecting rods, a first external pin and a first outer frame, the first lead frame The outer end of a connecting rod is connected with the first outer frame, the inner end is connected with the first chip holder, the outer end of the first outer pin is connected with the first outer frame, and the inner end is connected with the first outer frame. The gate of the chip placed on the first chip holder is turned on, and the bridge frame includes a second chip holder, a plurality of second connecting rods and a second outer frame, and the outer ends of the second connecting rods are connected to the second outer frame. The second outer frame is connected, and its inner end is connected to the second chip holder, and the lower side of the second chip holder is provided with a folded edge. When the bridge frame is stacked on the top of the first lead frame, the The bottom of the folded edge is on the same level as the lower surface of the first chip holder, and a space for bonding chips is provided between the first chip holder and the second chip holder.

The present application discloses a full-bridge overcurrent protection circuit and a full-bridge overcurrent protection method. The full-bridge overcurrent protection circuit includes a first gating module, a first comparator, a second gating module, a second comparator, and The logic control module, through the first gating module multiplexing the first comparator, can selectively determine whether the two upper bridge arms have overcurrent, and through the second gating module multiplexing the second comparator, it can selectively determine the two Whether overcurrent occurs in the lower bridge arm can reduce the number of comparators used to two, which greatly saves PCB space or integrated chip area.

The present invention relates to a fiber optic adapter for mating an opposing MT ferrule connectors. An adapter housing formed from a top portion and a bottom portion holds a pair of opposing MT ferrules. The adapter housing is stackable on its vertical side.

The present invention discloses an integrated surge immunity full-wave rectifier bridge structure. The structure comprises a plastic package body, four diode chips with the same technical indexes, anunidirectional TVS chip, and a first lead frame, a second lead frame, a third lead frame and a fourth lead frame; the unidirectional TVS chip has a P-type top surface, is fixed on the second lead frame, and is connected with the four lead frame through a wire; two of the four diode chips have P-type top surfaces, are fixed on the second lead frame and are respectively connected with the first leadframe and the third lead frame through wires; the other two of the four diode chips have N-type top surfaces, are fixed on the fourth lead frame, and are respectively connected with the first lead frame and the third lead frame through wires; and the first lead frame and the third lead frame are taken as input pins, and the second lead frame and the four lead frame are respectively taken as a positive pole pin and a negative pole pin. After the unidirectional TVS chip is arranged at a traditional rectifier bridge, the integrated surge immunity full-wave rectifier bridge structure is compact in layout, low in cost and thinner in thickness. The integrated surge immunity full-wave rectifier bridge structure is suitable for the technical field of electronic devices.

Disclosed is a memory thermal trip detecting method. The memory thermal trip detecting method is used for detecting thermal trip signals of a plurality of memories in a server and includes a setting step, a detecting step, a send request step, a receiving step, an analyzing step and a recording step, wherein the setting step includes that an identity (ID) number of each memory is set; the detecting step includes that whether thermal trip signals of a main memory of a gate output end are triggered or not is detected; the send request step includes that when the thermal trip signals of the main memory are detected to be triggered, a preset inquiry signal request is sent to inquire a thermal trip signal value of each memory in a complex programmable logic device (CPLD), and each input end of the CPLD is connected with a thermal trip signal output end of each memory; the receiving step includes that serial data of the thermal trip signals of all memories, which are sent by the CPLD according to a preset received signal coded format, are received; the analyzing step includes that the received serial data of the thermal trip signals of all memories are analyzed; the recording step includes that the memories with triggered thermal trip signals are recorded in a BMC journal according to the analyzed data. The invention further provides a memory thermal trip detecting system.

The invention discloses a module for starting multiple user programs by a single Flash. The module is characterized by comprising one programmable device and one FLASH chip connected with the programmable device, wherein multiple user program storage regions and one public program storage region are divided in the FLASH chip, each user program storage region stores one corresponding user program, and the public program storage region stores one corresponding EEPROM (Electrically Erasable Programmable Read-Only Memory) program; the programmable device can accept the access of multiple CPUs (Central Processing Units) and one FPGA (Field Programmable Gate Array) in parallel, thereby realizing that the public program storage region in the FLASH chip corresponds to the FPGA, and each user program storage region respectively corresponds to one CPU; and a bus switching module is designed in the programmable device, and the bus switching module can orderly transmit the user programs in the user program storage regions of the FLASH chip to the corresponding CPUs and transmit the EEPROM program to the corresponding FPGA.

The invention discloses a protection circuit of an automobile bus communication circuit. The protection circuit includes a communication interface circuit, an interface protection circuit and a protocol configuration matrix circuit; the signal output end of the communication interface circuit is connected with the input end of the communication interface protection circuit, and the output end of the communication interface protection circuit is connected with the input end of the protocol configuration matrix circuit. The invention provides the protection circuit of the automobile bus communication circuit, real-time overcurrent protection is achieved, the problems that the PTC reaction speed is low and protection is not complete and thorough are solved, compared with PTCs used in all circuits, the cost of several transistors and resistors is almost negligible, and at the same time, the occupied PCB space is shrunk. The protection circuit had the advantages that the circuit structure is simple, devices occupies small space, full protection is achieved rapidly in real time, and the cost is low.

The invention discloses a protection circuit of an automobile bus communication circuit. The protection circuit includes a communication interface circuit, an interface protection circuit and a protocol configuration matrix circuit; the signal output end of the communication interface circuit is connected with the input end of the communication interface protection circuit, and the output end of the communication interface protection circuit is connected with the input end of the protocol configuration matrix circuit. The invention provides the protection circuit of the automobile bus communication circuit, real-time overcurrent protection is achieved, the problems that the PTC reaction speed is low and protection is not complete and thorough are solved, compared with PTCs used in all circuits, the cost of several transistors and resistors is almost negligible, and at the same time, the occupied PCB space is shrunk. The protection circuit had the advantages that the circuit structure is simple, devices occupies small space, full protection is achieved rapidly in real time, and the cost is low.

The invention provides a digital signal transmission circuit and a digital signal transmission device. The digital signal transmission circuit comprises a power supply and sampling circuit, which is provided with a power supply output end and a signal sampling end; a voltage and current conversion circuit, which is connected to a power supply through the power supply output end of the power supply and sampling circuit, wherein the signal input end of the voltage and current conversion circuit is used for receiving digital signals, and the output end of the voltage and current conversion circuit is connected with the signal sampling end of the power supply and sampling circuit; and a signal output circuit, which is connected with the output end of the power supply and sampling circuit. According to the technical scheme, the anti-interference capability in the digital signal transmission process can be improved, and the reliability of digital signal transmission is improved.