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Equalization circuit, receiving circuit and semiconductor integrated circuit

A technology of equalizing circuits and circuits, which is applied to the shaping network, electrical components, line transmission components and other directions in the transmitter/receiver to achieve the effect of easing the timing and improving the action margin.

Active Publication Date: 2022-02-08
SOCIONEXT INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0008] in addition, Figure 7 The conventional floating-tap decision feedback equalization circuit 700 shown can expand the compensation range by increasing the number of D latch circuits 703, but increasing the number of D latch circuits 703 increases the load on the demultiplexer 704, Delay T mux get bigger

Method used

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  • Equalization circuit, receiving circuit and semiconductor integrated circuit
  • Equalization circuit, receiving circuit and semiconductor integrated circuit
  • Equalization circuit, receiving circuit and semiconductor integrated circuit

Examples

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no. 1 approach

[0024] A first embodiment of the present invention will be described.

[0025] figure 1 It is a diagram showing a configuration example of the equalization circuit 100 in the first embodiment. The equalizer circuit 100 is a floating-tap decision feedback equalizer circuit that compensates for the influence of any bit in a past bit string. The floating-tap decision feedback equalization circuit 100 has an addition circuit 101, a comparison circuit 102, a plurality of D latch circuits 103, a selection circuit (multiplexer) 104, a D latch circuit 105, a digital-to-analog (DA) conversion circuit 106 and logic circuit 107 .

[0026] The addition circuit 101 adds the compensation signal SG1 output from the DA conversion circuit 106 to the input data signal IDT according to a bit selected from the past bit string, and outputs it. The comparing circuit 102 compares the output of the adding circuit 101 . The comparison circuit 102 performs a binary decision on the output of the ad...

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Abstract

The invention relates to an equalizing circuit, a receiving circuit and a semiconductor integrated circuit. The equalizing circuit has: an adding circuit (101), which adds an input signal and a compensation signal; a comparing circuit (102), which compares the output of the adding circuit; a first latch Circuit (103), the quantity is one less than the number of taps of the equalization circuit, and maintains the output of the comparison circuit; the selection circuit (104), selects one of the outputs of the comparison circuit and each first latch circuit and output; a second latch circuit (105), maintaining the output of the selection circuit; and a digital-to-analog conversion circuit (106), generating a compensation signal based on the output of the second latch circuit, so that the output of the selection circuit is passed through the second The latch circuit is supplied to the digital-to-analog conversion circuit, shortens the delay of the compensation signal, and relaxes the feedback timing to the adding circuit.

Description

technical field [0001] The present invention relates to an equalizing circuit, a receiving circuit and a semiconductor integrated circuit. Background technique [0002] One of the equalizer circuits that compensates for the signal loss caused by the intersymbol interference (ISI: Inter Symbol Interference) caused by the influence of the bit string of the received data signal is a decision feedback equalizer circuit (DFE: Decision Feedback Equalizer) ( For example, refer to Patent Documents 1 and 2). The compensation in the decision feedback equalization circuit is based on the judgment result of the past bit string, and the floating tap decision feedback equalization circuit can compensate the influence caused by any bit in the bit string. [0003] Floating tap decision feedback equalization circuit such as Figure 7 As an example shown in , it includes an addition circuit 701 , a comparison circuit 702 , a plurality of D latch circuits 703 , a selection circuit (demultiple...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04L25/03H04B3/06
CPCH04B3/06H04B3/04H04L25/03146H04L2025/03484H04L25/03057H04L25/03H04L7/0058
Inventor 铃木大辅工藤真大
Owner SOCIONEXT INC